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SPP support beta
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BIITER
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a690b0b8f1
commit
15685182ae
4 changed files with 268 additions and 5 deletions
131
firmware/src/ssp.c
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131
firmware/src/ssp.c
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#include "LPC13xx.h"
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#include "ssp.h"
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void SSPSend( char *buf, uint32_t Length )
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{
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uint32_t i;
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uint8_t Dummy = Dummy;
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for ( i = 0; i < Length; i++ )
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{
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/* Move on only if NOT busy and TX FIFO not full. */
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while ( (LPC_SSP->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF );
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LPC_SSP->DR = *buf;
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buf++;
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#if !LOOPBACK_MODE
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while ( (LPC_SSP->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
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/* Whenever a byte is written, MISO FIFO counter increments, Clear FIFO
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on MISO. Otherwise, when SSP0Receive() is called, previous data byte
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is left in the FIFO. */
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Dummy = LPC_SSP->DR;
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#else
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/* Wait until the Busy bit is cleared. */
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while ( LPC_SSP->SR & SSPSR_BSY );
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#endif
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}
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return;
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}
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void SSPInit() {
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// reset peripherals
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LPC_SYSCON->PRESETCTRL |= (0x01<<0); // SSP reset de-asserted
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LPC_SYSCON->SYSAHBCLKCTRL |= (0x01<<11); // Enables clock for SSP.
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LPC_SYSCON->SSPCLKDIV = 2; // div clock by 2
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LPC_IOCON->PIO0_8 &= ~0x07; // ???
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LPC_IOCON->PIO0_8 |= 0x01; // MISO
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LPC_IOCON->PIO0_9 &= ~0x07; // ???
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LPC_IOCON->PIO0_9 |= 0x01; // MOSI
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#ifdef __JTAG_DISABLED
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LPC_IOCON->SCKLOC = 0x00;
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LPC_IOCON->SWCLK_PIO0_10 &= ~0x07;
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LPC_IOCON->SWCLK_PIO0_10 |= 0x02;>/* SSP CLK */
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#endif
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// This register is used to select a pin among three possible choices for the SSP SCK function.
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LPC_IOCON->SCKLOC = 1; // Selects SCK function for pin PIO2_11/SCK
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LPC_IOCON->PIO2_11 = 1;
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// set SSEL as GPIO that the master has total control of the sequence
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LPC_IOCON->PIO0_2 &= ~0x07;
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LPC_IOCON->PIO0_2 |= 0x01;
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// TODO ?????????????????????????????????
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LPC_SSP->CR0 = 0x0007;
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LPC_SSP->CPSR = 0x02;
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LPC_IOCON->PIO0_7 = 0x00; // D/C^
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LPC_GPIO0->DIR |= 1 << 7;
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LPC_IOCON->PIO2_0 = 0x00; // RES^
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LPC_GPIO2->DIR |= 1 << 0;
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// SSP Enable with Master mode
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LPC_SSP->CR1 = (0x01<<1) | (0x00<<2);
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NVIC_EnableIRQ(SSP_IRQn);
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/* Set SSPINMS registers to enable interrupts */
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/* enable all error related interrupts */
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LPC_SSP->IMSC = (0x1<<0) | (0x1<<1);
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int i;
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// reset
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//LPC_GPIO2->MASKED_ACCESS[0x01<<0] = 1 << 0;
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// for (i = 0; i < 100; i++);
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//LPC_GPIO2->MASKED_ACCESS[0x01<<0] = 0 << 0;
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// select
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//LPC_GPIO0->MASKED_ACCESS[0x01<<2] = 0 << 2;
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// for (i = 0; i < 100; i++);
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// command
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LPC_GPIO0->MASKED_ACCESS[0x01<<7] = 0 << 7;
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// for (i = 0; i < 100; i++);
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/*
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SSPSend("\x21\xc8\x06\x13\x20\x0c", 6);
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// x:0 y:0
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SSPSend("\x20\x0c", 2);
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SSPSend("\x80\x40", 2);
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// data
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LPC_GPIO0->MASKED_ACCESS[0x01<<7] = 0 << 7;
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// for (i = 0; i < 100; i++);
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SSPSend("\x21\xc8\x06\x13\x20\x0c", 6);
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// x:0 y:0
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SSPSend("\x20\x0c", 2);
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LPC_GPIO0->MASKED_ACCESS[0x01<<7] = 0 << 7;
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*/
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SSPSend("\x21\xc8\x06\x13\x20\x0c", 6);
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SSPSend("\x80\x40", 2);
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//SSPSend("\x20\x0c", 2);
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LPC_GPIO0->MASKED_ACCESS[0x01<<7] = 1 << 7;
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for (i=0;i<84*48;i++)
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SSPSend("\x00", 1);
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SSPSend("\x00", 1);
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SSPSend("\x00", 1);
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while (1){
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SSPSend("\x7f\x49\x49\x49\x36\x00", 6); // B
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SSPSend("\x7f\x09\x19\x29\x46\x00", 6); // R
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SSPSend("\x7f\x02\x0c\x02\x7f\x00", 6); // M
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SSPSend("\x7f\x40\x40\x40\x40\x00", 6); // L
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SSPSend("\x7e\x11\x11\x11\x7e\x00", 6); // A
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SSPSend("\x7f\x49\x49\x49\x36\x00", 6); // B
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SSPSend("\x00\x00\x00\x00\x00\x00\x00", 7);
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for(i=0;i<100000;i++);
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}
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}
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118
firmware/src/ssp.h
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118
firmware/src/ssp.h
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/****************************************************************************
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* $Id:: ssp.h 3632 2010-06-01 22:54:42Z usb00423 $
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* Project: NXP LPC13xx SSP example
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*
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* Description:
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* This file contains SSP code header definition.
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*
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****************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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****************************************************************************/
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#ifndef __SSP_H__
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#define __SSP_H__
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/* There are there modes in SSP: loopback, master or slave. */
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/* Here are the combination of all the tests.
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(1) LOOPBACK test: LOOPBACK_MODE=1, TX_RX_ONLY=0, USE_CS=1;
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(2) Serial EEPROM test: LOOPBACK_MODE=0, TX_RX_ONLY=0, USE_CS=0; (default)
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(3) TX(Master) Only: LOOPBACK_MODE=0, SSP_SLAVE=0, TX_RX_ONLY=1, USE_CS=1;
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(4) RX(Slave) Only: LOOPBACK_MODE=0, SSP_SLAVE=1, TX_RX_ONLY=0, USE_CS=1 */
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#define LOOPBACK_MODE 0 /* 1 is loopback, 0 is normal operation. */
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#define SSP_SLAVE 0 /* 1 is SLAVE mode, 0 is master mode */
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#define TX_RX_ONLY 0 /* 1 is TX or RX only depending on SSP_SLAVE
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flag, 0 is either loopback mode or communicate
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with a serial EEPROM. */
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/* if USE_CS is zero, set SSEL as GPIO that you have total control of the sequence */
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/* When test serial SEEPROM(LOOPBACK_MODE=0, TX_RX_ONLY=0), set USE_CS to 0. */
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/* When LOOPBACK_MODE=1 or TX_RX_ONLY=1, set USE_CS to 1. */
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#define USE_CS 0
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#define SSP_DEBUG 0
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/* SPI read and write buffer size */
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#define SSP_BUFSIZE 16
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#define FIFOSIZE 8
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#define DELAY_COUNT 10
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#define MAX_TIMEOUT 0xFF
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/* Port0.2 is the SSP select pin */
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#define SSP0_SEL (0x1<<2)
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/* SSP Status register */
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#define SSPSR_TFE (0x1<<0)
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#define SSPSR_TNF (0x1<<1)
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#define SSPSR_RNE (0x1<<2)
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#define SSPSR_RFF (0x1<<3)
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#define SSPSR_BSY (0x1<<4)
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/* SSP CR0 register */
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#define SSPCR0_DSS (0x1<<0)
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#define SSPCR0_FRF (0x1<<4)
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#define SSPCR0_SPO (0x1<<6)
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#define SSPCR0_SPH (0x1<<7)
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#define SSPCR0_SCR (0x1<<8)
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/* SSP CR1 register */
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#define SSPCR1_LBM (0x1<<0)
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#define SSPCR1_SSE (0x1<<1)
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#define SSPCR1_MS (0x1<<2)
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#define SSPCR1_SOD (0x1<<3)
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/* SSP Interrupt Mask Set/Clear register */
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#define SSPIMSC_RORIM (0x1<<0)
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#define SSPIMSC_RTIM (0x1<<1)
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#define SSPIMSC_RXIM (0x1<<2)
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#define SSPIMSC_TXIM (0x1<<3)
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/* SSP0 Interrupt Status register */
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#define SSPRIS_RORRIS (0x1<<0)
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#define SSPRIS_RTRIS (0x1<<1)
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#define SSPRIS_RXRIS (0x1<<2)
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#define SSPRIS_TXRIS (0x1<<3)
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/* SSP0 Masked Interrupt register */
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#define SSPMIS_RORMIS (0x1<<0)
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#define SSPMIS_RTMIS (0x1<<1)
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#define SSPMIS_RXMIS (0x1<<2)
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#define SSPMIS_TXMIS (0x1<<3)
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/* SSP0 Interrupt clear register */
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#define SSPICR_RORIC (0x1<<0)
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#define SSPICR_RTIC (0x1<<1)
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/* ATMEL SEEPROM command set */
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#define WREN 0x06 /* MSB A8 is set to 0, simplifying test */
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#define WRDI 0x04
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#define RDSR 0x05
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#define WRSR 0x01
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#define READ 0x03
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#define WRITE 0x02
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/* RDSR status bit definition */
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#define RDSR_RDY 0x01
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#define RDSR_WEN 0x02
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/* If RX_INTERRUPT is enabled, the SSP RX will be handled in the ISR
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SSPReceive() will not be needed. */
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extern void SSP_IRQHandler (void);
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extern void SSPInit( void );
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extern void SSPSend( char *Buf, uint32_t Length );
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extern void SSPReceive( uint8_t *buf, uint32_t Length );
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#endif /* __SSP_H__ */
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/*****************************************************************************
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** End Of File
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******************************************************************************/
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@ -21,6 +21,7 @@
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#include "gpio.h"
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#include "rom_drivers.h"
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#include "config.h"
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#include "ssp.h"
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#include <string.h>
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@ -64,10 +65,14 @@ int main (void)
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volatile int n;
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// Code Red Red Suite and LPCXpresso by Code Red both call SystemInit() in
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// the C startup code
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#ifndef __CODERED__
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//#ifndef __CODERED__
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SystemInit();
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#endif
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//#endif
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/*
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LPC_GPIO2->MASKED_ACCESS[0x01<<0] = 1 << 0;
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SSPSend("BIITER", 6);
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*/
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HidDevInfo.idVendor = USB_VENDOR_ID;
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HidDevInfo.idProduct = USB_PROD_ID;
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@ -86,7 +91,7 @@ int main (void)
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LPC_SYSCON->SYSAHBCLKCTRL |= (EN_TIMER32_1 | EN_IOCON | EN_USBREG);
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/* Use pll and pin init function in rom */
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(*rom)->pUSBD->init_clk_pins();
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(*rom)->pUSBD->init_clk_pins();
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/* insert a delay between clk init and usb init */
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for (n = 0; n < 75; n++) {}
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@ -94,6 +99,8 @@ int main (void)
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(*rom)->pUSBD->init(&DeviceInfo); /* USB Initialization */
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(*rom)->pUSBD->connect(TRUE); /* USB Connect */
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SSPInit();
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while (1)
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__WFI();
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}
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@ -106,3 +113,10 @@ void USB_IRQHandler()
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{
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(*rom)->pUSBD->isr();
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}
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void SSP_IRQHandler(void)
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{
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while(1)
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{
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}
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}
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