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Added ADC and I/O read.

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BIITER 2011-04-08 19:43:52 +02:00
parent b9d7328f20
commit 2b9ef9759b
8 changed files with 391 additions and 24 deletions
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55
firmware/src/edubrm.c
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@ -1,6 +1,7 @@
#include "config.h"
#include "LPC13xx.h"
#include "ssp.h"
#include "adc.h"
#include "chars.h"
#include "pbjt.h"
@ -56,3 +57,57 @@ void SetOutReport (uint8_t dst[], uint32_t length)
}
}
}
//static uint8_t x = 0;
void TIMER32_0_IRQHandler(void) {
LPC_TMR32B0->IR = 0xff; // clear interrupt
/*
uint32_t x = LPC_TMR32B0->EMR & 1 ? 0xff : 0;
SSPSend((uint8_t*)&x, 1);
*/
/*
uint32_t x = ADCRead(0);
uint8_t z = 0;
if (x >= 0) z = 0x01;
if (x >= 32) z = 0x02;
if (x >= 64) z = 0x04;
if (x >= 96) z = 0x08;
if (x >= 128) z = 0x10;
if (x >= 160) z = 0x20;
if (x >= 192) z = 0x40;
if (x >= 256) z = 0x80;
z |= 0x80;
SSPSend(&z, 1);
*/
// read PIO3_3
uint8_t x = LPC_GPIO3->MASKED_ACCESS[1<<3];
x = (x&(1<<3)) ? 0xff : 0;
SSPSend(&x, 1);
}
void PWMRun(void) {
LPC_SYSCON->SYSAHBCLKCTRL |= 1<<9; // Enables clock for 32-bit counter/timer 0.
LPC_IOCON->PIO1_6 &= ~0x07;
LPC_IOCON->PIO1_6 |= 0x02; // Selects function CT32B0_MAT0
LPC_TMR32B0->MR3 = 4294967; // period
LPC_TMR32B0->MR0 = 4294967/2; // duty
LPC_TMR32B0->MCR = 1<<10; // Reset on MR3: the TC will be reset if MR3 matches it.
LPC_TMR32B0->EMR = 3<<4; // Toggle the corresponding External Match bit/output.
LPC_TMR32B0->PWMC = 1<<0 | 1<<3; // enable pwn
LPC_TMR32B0->MCR |= 1<<9| 1<<0; NVIC_EnableIRQ(TIMER_32_0_IRQn);
LPC_TMR32B0->TCR = 1;
}