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implement first prototype of the protocol
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parent
f30c462567
commit
4fb8173118
2 changed files with 39 additions and 7 deletions
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@ -5,7 +5,9 @@ class Device:
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VENDORID = 0x1fc9
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PRODUCTID = 0x1337
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INSIZE = 64
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OUTSIZE = 2
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OUTSIZE = 64
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polling = 0
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def __init__(self):
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usbdev = usb.core.find(idVendor = self.VENDORID, idProduct = self.PRODUCTID)
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@ -23,10 +25,40 @@ class Device:
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custom_match = lambda e: \
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usb.util.endpoint_direction(e.bEndpointAddress) == usb.util.ENDPOINT_IN)
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# TODO: PWM
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# TODO: SPI
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# TODO: SET/CLEAR PINS
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# sets pwm (which=1,2), (percent=16bit)
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def pwm(self, which, percent):
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self.epo.write('p' + chr(which) + chr(percent & 0xff) + chr(percent >> 8))
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# sets dds (wave=square,sine,saw1,saw2), (freq=24bit)
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def dds(self, wave, freq):
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self.epo.write('d' + chr(wave) + chr(freq & 0xff) + chr((freq >> 8) & 0xff) + chr((freq >> 16) & 0xff))
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# set opamp (which=1,2), (chan=6), (mult=16bit?)
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def opamp(self, which, chan, mult):
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self.epo.write('o' + chr(which) + chr(chan) + chr(mult & 0xff) + chr(percent >> 8))
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# set switch (which=1..8), state=(0,1)
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def switch(self, which, state):
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self.epo.write('s' + chr(which) + (state and '\x01' or '\x00'))
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# set all switches (states=8bit)
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def switches(self, states):
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self.epo.write('S' + chr(states))
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# clear output (which=8bit)
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def clrout(self, which):
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self.epo.write('o' + chr(which))
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# set output (which=8bit)
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def setout(self, which):
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self.epo.write('O' + chr(which))
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def pollfreq(self, freq):
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self.polling = freq
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def state(self):
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# TODO: format?
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return self.epi.read(self.INSIZE)
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# 4x AD (16 bits) + 8x I
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i = self.epi.read(self.INSIZE)
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return (i[0] + i[1]<<8, i[2] + i[3]<<8, i[4] + i[5]<<8, i[6] + i[7]<<8,
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i[8] & 0x01, i[8] & 0x02, i[8] & 0x04, i[8] & 0x08,
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i[8] & 0x10, i[8] & 0x20, i[8] & 0x40, i[8] & 0x80)
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