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debug module almost done
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75704ff29f
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5 changed files with 682 additions and 259 deletions
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@ -27,33 +27,33 @@ class Device:
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def pwm(self, which, duty):
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self.epo.write('p' + chr(which) + chr(duty & 0xff) + chr(duty >> 8))
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# sets dds (wave=square,sine,saw1,saw2), (freq=32bit)
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def dds(self, wavetype, freq):
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self.epo.write('d' + chr(wavetype) + chr(freq & 0xff) + chr((freq >> 8) & 0xff) + chr((freq >> 16) & 0xff) + chr(freq >> 24))
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# sets ddswave (wave=square,sine,saw1,saw2)
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def ddswave(self, wavetype):
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self.epo.write('d' + chr(wavetype))
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# set opamp (which=1,2), (mult=16bit)
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def opamp(self, which, mult):
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self.epo.write('m' + chr(which) + chr(mult & 0xff) + chr(mult >> 8))
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# sets ddsfreq (freq=32bit)
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def ddsfreq(self, freq):
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self.epo.write('D' + chr(freq & 0xff) + chr((freq >> 8) & 0xff) + chr((freq >> 16) & 0xff) + chr(freq >> 24))
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# set switch (which=1..8), state=(0,1)
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def switch(self, which, state):
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self.epo.write('s' + chr(which) + (state and '\x01' or '\x00'))
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# set opamp (which=1,2), (chan=1..6), (gain=1, 2, 4, 5, 8, 10, 16, 32)
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def opamp(self, which, chan, gain):
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self.epo.write('m' + chr(which) + chr(chan) + chr(gain))
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# set all switches (which=8bit)
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# set all switches (states=6bit)
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def switches(self, states):
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self.epo.write('S' + chr(states))
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self.epo.write('s' + chr(states))
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# clear output (which=8bit)
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def clrout(self, which):
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self.epo.write('o' + chr(which))
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# set pins state (states=3bit) (1 = input, 0 = output)
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def setpins(self, states):
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self.epo.write('P' + chr(states))
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# set output (which=8bit)
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def setout(self, which):
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self.epo.write('O' + chr(which))
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# set output (which=1,2,3), (state=0,1)
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def setout(self, which, state):
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self.epo.write('o' + chr(which<<1 + state))
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def state(self):
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# 4x AD (16 bits) + 8x I
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def read(self):
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# 6x AD (16 bits) + 3 x I
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i = self.epi.read(self.INSIZE)
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return (i[0] + i[1]<<8, i[2] + i[3]<<8, i[4] + i[5]<<8, i[6] + i[7]<<8,
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i[8] & 0x01, i[8] & 0x02, i[8] & 0x04, i[8] & 0x08,
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i[8] & 0x10, i[8] & 0x20, i[8] & 0x40, i[8] & 0x80)
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return (i[0] + i[1]<<8, i[2] + i[3]<<8, i[4] + i[5]<<8,
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i[6] + i[7]<<8, i[9] + i[9]<<8, i[10] + i[11]<<8,
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i[12] & 0x01, (i[12] & 0x02) >> 1, (i[12] & 0x04) >> 2)
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