diff --git a/firmware/CMSISv1p30_LPC13xx/.cproject b/firmware/CMSISv1p30_LPC13xx/.cproject index cb0ab48..096a09f 100644 --- a/firmware/CMSISv1p30_LPC13xx/.cproject +++ b/firmware/CMSISv1p30_LPC13xx/.cproject @@ -1,889 +1,889 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1311" property_count="5" version="1"/> -<infoList vendor="NXP"> -<info chip="LPC1311" match_id="0x2c42502b" name="LPC1311" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC1311</name> -<family>LPC13xx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash8" location="0x00000000" size="0x2000"/> -<memoryInstance derived_from="RAM" id="RamLoc2" location="0x10000000" size="0x800"/> -<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x400" progwithcode="TRUE" size="0x2000"/> -<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> -<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40004000"/> -<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> -<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP" location="0x40040000"/> -<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> -<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> -<peripheralInstance derived_from="LPC13_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> -<peripheralInstance derived_from="LPC11_13_PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="LPC11_13_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> -<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> -</chip> -<processor> -<name gcc_name="cortex-m3">Cortex-M3</name> -<family>Cortex-M</family> -</processor> -<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig> - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1311" property_count="5" version="1"/> +<infoList vendor="NXP"> +<info chip="LPC1311" match_id="0x2c42502b" name="LPC1311" stub="crt_emu_lpc11_13_nxp"> +<chip> +<name>LPC1311</name> +<family>LPC13xx</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash8" location="0x00000000" size="0x2000"/> +<memoryInstance derived_from="RAM" id="RamLoc2" location="0x10000000" size="0x800"/> +<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x400" progwithcode="TRUE" size="0x2000"/> +<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40004000"/> +<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> +<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP" location="0x40040000"/> +<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> +<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> +<peripheralInstance derived_from="LPC13_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> +<peripheralInstance derived_from="LPC11_13_PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="LPC11_13_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> +<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> +</chip> +<processor> +<name gcc_name="cortex-m3">Cortex-M3</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + diff --git a/firmware/CMSISv1p30_LPC13xx/.project b/firmware/CMSISv1p30_LPC13xx/.project index b21d0a8..0adf94f 100644 --- a/firmware/CMSISv1p30_LPC13xx/.project +++ b/firmware/CMSISv1p30_LPC13xx/.project @@ -1,81 +1,81 @@ - - - CMSISv1p30_LPC13xx - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/CMSISv1p30_LPC13xx/Debug} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.core.cnature - - + + + CMSISv1p30_LPC13xx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/CMSISv1p30_LPC13xx/Debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + diff --git a/firmware/CMSISv1p30_LPC13xx/cmsis_readme.txt b/firmware/CMSISv1p30_LPC13xx/cmsis_readme.txt index 2ce3bc2..d345055 100644 --- a/firmware/CMSISv1p30_LPC13xx/cmsis_readme.txt +++ b/firmware/CMSISv1p30_LPC13xx/cmsis_readme.txt @@ -1,28 +1,28 @@ -CMSIS : Cortex Microcontroller Software Interface Standard -========================================================== -CMSIS defines for a Cortex-M Microcontroller System: - - * A common way to access peripheral registers and a - common way to define exception vectors. - * The register names of the Core Peripherals and the - names of the Core Exception Vectors. - * An device independent interface for RTOS Kernels - including a debug channel. - -By using CMSIS compliant software components, the user can -easier re-use template code. CMSIS is intended to enable the -combination of software components from multiple middleware -vendors. - -This project contains appropriate files for this MCU family -taken from CMSIS. A full copy of the CMSIS files can be found -within your tools installation directory. More information on -CMSIS can be found at: - - http://www.onarm.com/ - http://www.arm.com/ - - - - - +CMSIS : Cortex Microcontroller Software Interface Standard +========================================================== +CMSIS defines for a Cortex-M Microcontroller System: + + * A common way to access peripheral registers and a + common way to define exception vectors. + * The register names of the Core Peripherals and the + names of the Core Exception Vectors. + * An device independent interface for RTOS Kernels + including a debug channel. + +By using CMSIS compliant software components, the user can +easier re-use template code. CMSIS is intended to enable the +combination of software components from multiple middleware +vendors. + +This project contains appropriate files for this MCU family +taken from CMSIS. A full copy of the CMSIS files can be found +within your tools installation directory. More information on +CMSIS can be found at: + + http://www.onarm.com/ + http://www.arm.com/ + + + + + diff --git a/firmware/CMSISv1p30_LPC13xx/docs/CMSIS changes.htm b/firmware/CMSISv1p30_LPC13xx/docs/CMSIS changes.htm deleted file mode 100644 index 162ffcc..0000000 --- a/firmware/CMSISv1p30_LPC13xx/docs/CMSIS changes.htm +++ /dev/null @@ -1,320 +0,0 @@ - - - -CMSIS Changes - - - - - - - - -

Changes to CMSIS version V1.20

- -
- -

1. Removed CMSIS Middelware packages

-

- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. -

- -

2. SystemFrequency renamed to SystemCoreClock

-

- The variable name SystemCoreClock is more precise than SystemFrequency - because the variable holds the clock value at which the core is running. -

- -

3. Changed startup concept

-

- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit - from main) has the weakness that it does not work for controllers which need a already - configuerd clock system to configure the external memory controller. -

- -

Changed startup concept

- - - -

4. Advanced Debug Functions

-

- ITM communication channel is only capable for OUT direction. To allow also communication for - IN direction a simple concept is provided. -

- - -

- For detailed explanation see file CMSIS debug support.htm. -

- - -

5. Core Register Bit Definitions

-

- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the - defines correspond with the Cortex-M Technical Reference Manual. -

-

- e.g. SysTick structure with bit definitions -

-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
- -

7. DoxyGen Tags

-

- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation - using DoxyGen. -

- -

8. Folder Structure

-

- The folder structure is changed to differentiate the single support packages. -

- - - -

9. Open Points

-

- Following points need to be clarified and solved: -

- - - -

10. Limitations

-

- The following limitations are not covered with the current CMSIS version: -

- diff --git a/firmware/CMSISv1p30_LPC13xx/docs/CMSIS debug support.htm b/firmware/CMSISv1p30_LPC13xx/docs/CMSIS debug support.htm deleted file mode 100644 index efda685..0000000 --- a/firmware/CMSISv1p30_LPC13xx/docs/CMSIS debug support.htm +++ /dev/null @@ -1,243 +0,0 @@ - - - -CMSIS Debug Support - - - - - - - - -

CMSIS Debug Support

- -
- -

Cortex-M3 ITM Debug Access

-

- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with - the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has - 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM - communication channels are used by CMSIS to output the following information: -

- - -

Debug IN / OUT functions

-

CMSIS provides following debug functions:

- - -

ITM_SendChar

-

- ITM_SendChar is used to transmit a character over ITM channel 0 from - the microcontroller system to the debug system.
- Only a 8 bit value is transmitted. -

-
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  /* check if debugger connected and ITM channel enabled for tracing */
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
-      (ITM->TCR & ITM_TCR_ITMENA)                  &&
-      (ITM->TER & (1UL << 0))  ) 
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }  
-  return (ch);
-}
- -

ITM_ReceiveChar

-

- ITM communication channel is only capable for OUT direction. For IN direction - a globel variable is used. A simple mechansim detects if a character is received. - The project to test need to be build with debug information. -

- -

- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system - to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake. -

-
-extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */
-
-

- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty - or contains a valid value. -

-
-#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-

- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking. - It returns the received character or '-1' if no character was available. -

-
-static __INLINE int ITM_ReceiveChar (void) {
-  int ch = -1;                               /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-  
-  return (ch); 
-}
-
- -

ITM_CheckChar

-

- ITM_CheckChar is used to check if a character is received. -

-
-static __INLINE int ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
- - -

ITM Debug Support in uVision

-

- uVision uses in a debug session the Debug (printf) Viewer window to - display the debug data. -

-

Direction microcontroller system -> uVision:

- - -

Direction uVision -> microcontroller system:

- - -

Note

- - -

RTX Kernel awareness in uVision

-

- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness. - No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access - to ITM communication channel 31. -

- -

Following RTX events are traced:

- - -

Note

- - - -

 

- -
- -

Copyright © KEIL - An ARM Company.
-All rights reserved.
-Visit our web site at www.keil.com. -

- - - - \ No newline at end of file diff --git a/firmware/CMSISv1p30_LPC13xx/docs/CMSIS_Core.htm b/firmware/CMSISv1p30_LPC13xx/docs/CMSIS_Core.htm deleted file mode 100644 index 6fd131e..0000000 --- a/firmware/CMSISv1p30_LPC13xx/docs/CMSIS_Core.htm +++ /dev/null @@ -1,1337 +0,0 @@ - - - - CMSIS: Cortex Microcontroller Software Interface Standard - - - -

Cortex Microcontroller Software Interface Standard

- -

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

-

Version: 1.30 - 30. October 2009

- -

Information in this file, the accompany manuals, and software is
- Copyright © ARM Ltd.
All rights reserved. -

- -
- -

Revision History

- - -
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Contents

- -
    -
  1. About
  2. -
  3. Coding Rules and Conventions
  4. -
  5. CMSIS Files
  6. -
  7. Core Peripheral Access Layer
  8. -
  9. CMSIS Example
  10. -
- -

About

- -

- The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges - that are faced when software components are deployed to physical microcontroller devices based on a - Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M - processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation - with various silicon and software vendors and provides a common approach to interface to peripherals, - real-time operating systems, and middleware components. -

- -

ARM provides as part of the CMSIS the following software layers that are -available for various compiler implementations:

- - -

These software layers are expanded by Silicon partners with:

- - -

CMSIS defines for a Cortex-M Microcontroller System:

- - -

- By using CMSIS compliant software components, the user can easier re-use template code. - CMSIS is intended to enable the combination of software components from multiple middleware vendors. -

- -

Coding Rules and Conventions

- -

- The following section describes the coding rules and conventions used in the CMSIS - implementation. It contains also information about data types and version number information. -

- -

Essentials

- - -

Recommendations

- -

The CMSIS recommends the following conventions for identifiers.

- - -Comments - - - -

Data Types and IO Type Qualifiers

- -

- The Cortex-M HAL uses the standard types from the standard ANSI C header file - <stdint.h>. IO Type Qualifiers are used to specify the access - to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of - debug information of peripheral registers. -

- - - - - - - - - - - - - - - - - - - - - - - - -
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access
- -

CMSIS Version Number

-

- File core_cm3.h contains the version number of the CMSIS with the following define: -

- -
-#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
-#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
- -

- File core_cm0.h contains the version number of the CMSIS with the following define: -

- -
-#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
-#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
- - -

CMSIS Cortex Core

-

- File core_cm3.h contains the type of the CMSIS Cortex-M with the following define: -

- -
-#define __CORTEX_M                (0x03)
- -

- File core_cm0.h contains the type of the CMSIS Cortex-M with the following define: -

- -
-#define __CORTEX_M                (0x00)
- - -

CMSIS Files

-

- This section describes the Files provided in context with the CMSIS to access the Cortex-M - hardware and peripherals. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use - several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm0.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
core_cm3.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes - typically the oscillator (PLL) that is part of the microcontroller device
- -

device.h

- -

- The file device.h is provided by the silicon vendor and is the - central include file that the application programmer is using in - the C source code. This file contains: -

- - - -

Interrupt Number Definition

- -

To access the device specific interrupts the device.h file defines IRQn -numbers for the complete device using a enum typedef as shown below:

-
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
-  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
-  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
-  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
-  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
-  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
-  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
-  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
-  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
-  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
-/******  STM32 specific Interrupt Numbers ****************************************************************/
-  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
-  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
-  :
-  :
-  } IRQn_Type;
- - -

Configuration for core_cm0.h / core_cm3.h

-

- The Cortex-M core configuration options which are defined for each device implementation. Some - configuration options are reflected in the CMSIS layer using the #define settings described below. -

-

- To access core peripherals file device.h includes file core_cm0.h / core_cm3.h. - Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be - defined before #include <core_cm0.h> / #include <core_cm3.h> - preprocessor command. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#defineFileValueDescription
__NVIC_PRIO_BITScore_cm0.h(2)Number of priority bits implemented in the NVIC (device specific)
__NVIC_PRIO_BITScore_cm3.h(2 ... 8)Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTcore_cm0.h, core_cm3.h(0, 1)Defines if an MPU is present or not
__Vendor_SysTickConfigcore_cm0.h, core_cm3.h(1)When this define is setup to 1, the SysTickConfig function - in core_cm3.h is excluded. In this case the device.h - file must contain a vendor specific implementation of this function.
- - -

Device Peripheral Access Layer

-

- Each peripheral uses a prefix which consists of <device abbreviation>_ - and <peripheral name>_ to identify peripheral registers that access this - specific peripheral. The intention of this is to avoid name collisions caused - due to short names. If more than one peripheral of the same type exists, - identifiers have a postfix (digit or letter). For example: -

- - -
Minimal Requiements
-

- To access the peripheral registers and related function in a device the files device.h - and core_cm0.h / core_cm3.h defines as a minimum: -

- - -

- These definitions allow to access the peripheral registers from user code with simple assignments like: -

-
SysTick->CTRL = 0;
- -
Optional Features
-

In addition the device.h file may define:

- - -

core_cm0.h and core_cm0.c

-

- File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does - the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers - and core peripherals with efficient functions (defined as static inline). -

-

- File core_cm0.c defines several helper functions that access processor registers. -

-

Together these files implement the Core Peripheral Access Layer for a Cortex-M0.

- -

core_cm3.h and core_cm3.c

-

- File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does - the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers - and core peripherals with efficient functions (defined as static inline). -

-

- File core_cm3.c defines several helper functions that access processor registers. -

-

Together these files implement the Core Peripheral Access Layer for a Cortex-M3.

- -

startup_device

-

- A template file for startup_device is provided by ARM for each supported - compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific - interrupt handlers. Each interrupt handler is defined as weak function - to an dummy handler. Therefore the interrupt handler can be directly used in application software - without any requirements to adapt the startup_device file. -

-

- The following exception names are fixed and define the start of the vector table for a Cortex-M0: -

-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
- -

- The following exception names are fixed and define the start of the vector table for a Cortex-M3: -

-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
- -

- In the following examples for device specific interrupts are shown: -

-
-; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler         ; Tamper
- -

- Device specific interrupts must have a dummy function that can be overwritten in user code. - Below is an example for this dummy function. -

-
-Default_Handler PROC
-                EXPORT WWDG_IRQHandler   [WEAK]
-                EXPORT PVD_IRQHandler    [WEAK]
-                EXPORT TAMPER_IRQHandler [WEAK]
-                :
-                :
-                WWDG_IRQHandler
-                PVD_IRQHandler
-                TAMPER_IRQHandler
-                :
-                :
-                B .
-                ENDP
- -

- The user application may simply define an interrupt handler function by using the handler name - as shown below. -

-
-void WWDG_IRQHandler(void)
-{
-  :
-  :
-}
- - -

system_device.c

-

- A template file for system_device.c is provided by ARM but adapted by - the silicon vendor to match their actual device. As a minimum requirement - this file must provide a device specific system configuration function and a global variable - that contains the system frequency. It configures the device and initializes typically the - oscillator (PLL) that is part of the microcontroller device. -

-

- The file system_device.c must provide - as a minimum requirement the SystemInit function as shown below. -

- - - - - - - - - - - - - - - - -
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the - oscillator (PLL) that is part of the microcontroller device. For systems - with variable clock speed it also updates the variable SystemCoreClock.
- SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void)Updates the variable SystemCoreClock and must be called whenever the - core clock is changed during program execution. SystemCoreClockUpdate() - evaluates the clock register settings and calculates the current core clock. -
- -

- Also part of the file system_device.c - is the variable SystemCoreClock which contains the current CPU clock speed shown below. -

- - - - - - - - - - - - -
Variable DefinitionDescription
uint32_t SystemCoreClockContains the system core clock (which is the system clock frequency supplied - to the SysTick timer and the processor core clock). This variable can be - used by the user application to setup the SysTick timer or configure other - parameters. It may also be used by debugger to query the frequency of the - debug timer or configure the trace clock speed.
- SystemCoreClock is initialized with a correct predefined value.

- The compiler must be configured to avoid the removal of this variable in - case that the application program is not using it. It is important for - debug systems that the variable is physically present in memory so that - it can be examined to configure the debugger.
- -

Note

- - - -

Core Peripheral Access Layer

- -

Cortex-M Core Register Access

-

- The following functions are defined in core_cm0.h / core_cm3.h - and provide access to Cortex-M core registers. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3PRIMASK = 0Global Interrupt enable (using the instruction CPSIE - i)
void __disable_irq (void)M0, M3PRIMASK = 1Global Interrupt disable (using the instruction - CPSID i)
void __set_PRIMASK (uint32_t value)M0, M3PRIMASK = valueAssign value to Priority Mask Register (using the instruction - MSR)
uint32_t __get_PRIMASK (void)M0, M3return PRIMASKReturn Priority Mask Register (using the instruction - MRS)
void __enable_fault_irq (void)M3FAULTMASK = 0Global Fault exception and Interrupt enable (using the - instruction CPSIE - f)
void __disable_fault_irq (void)M3FAULTMASK = 1Global Fault exception and Interrupt disable (using the - instruction CPSID f)
void __set_FAULTMASK (uint32_t value)M3FAULTMASK = valueAssign value to Fault Mask Register (using the instruction - MSR)
uint32_t __get_FAULTMASK (void)M3return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3BASEPRI = valueSet Base Priority (using the instruction MSR)
uiuint32_t __get_BASEPRI (void)M3return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_CONTROL (void)M0, M3return CONTROLReturn Control Register Value (using the instruction - MRS)
void __set_PSP (uint32_t TopOfProcStack)M0, M3PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction - MSR)
uint32_t __get_PSP (void)M0, M3return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3return MSPReturn Main Stack Pointer (using the instruction MRS)
- -

Cortex-M Instruction Access

-

- The following functions are defined in core_cm0.h / core_cm3.hand - generate specific Cortex-M instructions. The functions are implemented in the file - core_cm0.c / core_cm3.c. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameCoreGenerated CPU InstructionDescription
void __NOP (void)M0, M3NOPNo Operation
void __WFI (void)M0, M3WFIWait for Interrupt
void __WFE (void)M0, M3WFEWait for Event
void __SEV (void)M0, M3SEVSet Event
void __ISB (void)M0, M3ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3DSBData Synchronization Barrier
void __DMB (void)M0, M3DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3REV16Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value)M0, M3REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3LDREXWLoad exclusive word
uint32_t __STREXB (uint8_t value, uint8_t *addr)M3STREXBStore exclusive byte
uint32_t __STREXB (uint16_t value, uint16_t *addr)M3STREXHStore exclusive half-word
uint32_t __STREXB (uint32_t value, uint32_t *addr)M3STREXWStore exclusive word
void __CLREX (void)M3CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
- - -

NVIC Access Functions

-

- The CMSIS provides access to the NVIC via the register interface structure and several helper - functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to - identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative - IRQn values are used for processor core exceptions. -

-

- For the IRQn values of core exceptions the file device.h provides - the following enum names. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3-14Cortex-M Non Maskable Interrupt
HardFault_IRQnM0, M3-13Cortex-M Hard Fault Interrupt
MemoryManagement_IRQnM3-12Cortex-M Memory Management Interrupt
BusFault_IRQnM3-11Cortex-M Bus Fault Interrupt
UsageFault_IRQnM3-10Cortex-M Usage Fault Interrupt
SVCall_IRQnM0, M3-5Cortex-M SV Call Interrupt
DebugMonitor_IRQnM3-4Cortex-M Debug Monitor Interrupt
PendSV_IRQnM0, M3-2Cortex-M Pend SV Interrupt
SysTick_IRQnM0, M3-1Cortex-M System Tick Interrupt
- -

The following functions simplify the setup of the NVIC. -The functions are defined as static inline.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameCoreParameterDescription
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)M3Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void)M3(void)Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberEnable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberReturn 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3IRQ NumberReturn 1 if IRQn is active else 0
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)M0, M3IRQ Number, PrioritySet Priority for IRQn
- (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3IRQ NumberGet Priority for IRQn
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)M3IRQ Number, Priority Group, Preemptive Priority, Sub PriorityEncode priority for given group, preemptive and sub priority
NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)M3IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub PriorityDeccode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void)M0, M3(void)Resets the System
-

Note

- - - -

SysTick Configuration Function

- -

The following function is used to configure the SysTick timer and start the -SysTick interrupt.

- - - - - - - - - - - - - - -
NameParameterDescription
uint32_t SysTickConfig - (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this - call the SysTick timer creates interrupts with the specified time - interval.
-
- Return: 0 when successful, 1 on failure.
-
- - -

Cortex-M3 ITM Debug Access

- -

The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that -provides together with the Serial Viewer Output trace capabilities for the -microcontroller system. The ITM has 32 communication channels; two ITM -communication channels are used by CMSIS to output the following information:

- -

Note

- - -

The prototype of the ITM_SendChar routine is shown in the -table below.

- - - - - - - - - - - - - - -
NameParameterDescription
void uint32_t ITM_SendChar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The - function returns when no debugger is connected that has booked the - output. It is blocking when a debugger is connected, but the - previous character send is not transmitted.

- Return: the input character 'chr'.
- -

- Example for the usage of the ITM Channel 31 for RTOS Kernels: -

-
-  // check if debugger connected and ITM channel enabled for tracing
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
-  (ITM->TCR & ITM_TCR_ITMENA) &&
-  (ITM->TER & (1UL << 31))) {
-    // transmit trace data
-    while (ITM->PORT31_U32 == 0);
-    ITM->PORT[31].u8 = task_id;      // id of next task
-    while (ITM->PORT[31].u32 == 0);
-    ITM->PORT[31].u32 = task_status; // status information
-  }
- - -

Cortex-M3 additional Debug Access

- -

CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. -Data can be transmitted via a certain global buffer variable towards the target system.

- -

The buffer variable and the prototypes of the additional functions are shown in the -table below.

- - - - - - - - - - - - - - - - - - - - - - - - -
NameParameterDescription
extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system.

- Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in - ITM_RxBuffer.

- Return: -1 indicates that no character was received.
int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer.

- Return: 1 indicates that a character is available, 0 indicates that - no character is available.
- - -

CMSIS Example

-

- The following section shows a typical example for using the CMSIS layer in user applications. - The example is based on a STM32F10x Device. -

-
-#include "stm32f10x.h"
-
-volatile uint32_t msTicks;                       /* timeTicks counter */
-
-void SysTick_Handler(void) {
-  msTicks++;                                     /* increment timeTicks counter */
-}
-
-__INLINE static void Delay (uint32_t dlyTicks) {
-  uint32_t curTicks = msTicks;
-
-  while ((msTicks - curTicks) < dlyTicks);
-}
-
-__INLINE static void LED_Config(void) {
-  ;                                              /* Configure the LEDs */
-}
-
-__INLINE static void LED_On (uint32_t led) {
-  ;                                              /* Turn On  LED */
-}
-
-__INLINE static void LED_Off (uint32_t led) {
-  ;                                              /* Turn Off LED */
-}
-
-int main (void) {
-  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
-    ;                                            /* Handle Error */
-    while (1);
-  }
-  
-  LED_Config();                                  /* configure the LEDs */                            
- 
-  while(1) {
-    LED_On (0x100);                              /* Turn  on the LED   */
-    Delay (100);                                 /* delay  100 Msec    */
-    LED_Off (0x100);                             /* Turn off the LED   */
-    Delay (100);                                 /* delay  100 Msec    */
-  }
-}
- - - \ No newline at end of file diff --git a/firmware/CMSISv1p30_LPC13xx/docs/License.doc b/firmware/CMSISv1p30_LPC13xx/docs/License.doc deleted file mode 100644 index b6b8ace..0000000 Binary files a/firmware/CMSISv1p30_LPC13xx/docs/License.doc and /dev/null differ diff --git a/firmware/CMSISv1p30_LPC13xx/history.txt b/firmware/CMSISv1p30_LPC13xx/history.txt index f5a3639..3950ecf 100644 --- a/firmware/CMSISv1p30_LPC13xx/history.txt +++ b/firmware/CMSISv1p30_LPC13xx/history.txt @@ -1,12 +1,12 @@ -History of updates to CMSISv1p30_LPC13xx -======================================== - -18 February 2010 ----------------- -system_LPC13xx.c updated to new version (dated 18 February 2010), -changing value of SYSPLLCTRL_Val from 0x05 to 0x25 - -23 March 2010 -------------- -Optimisation level of release build of project changed from --O2 to -Os. +History of updates to CMSISv1p30_LPC13xx +======================================== + +18 February 2010 +---------------- +system_LPC13xx.c updated to new version (dated 18 February 2010), +changing value of SYSPLLCTRL_Val from 0x05 to 0x25 + +23 March 2010 +------------- +Optimisation level of release build of project changed from +-O2 to -Os. diff --git a/firmware/CMSISv1p30_LPC13xx/inc/LPC13xx.h b/firmware/CMSISv1p30_LPC13xx/inc/LPC13xx.h index e428164..81a9b5f 100644 --- a/firmware/CMSISv1p30_LPC13xx/inc/LPC13xx.h +++ b/firmware/CMSISv1p30_LPC13xx/inc/LPC13xx.h @@ -1,493 +1,493 @@ -/**************************************************************************//** - * @file LPC13xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * NXP LPC13xx Device Series - * @version V1.01 - * @date 19. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC13xx_H__ -#define __LPC13xx_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC13xx Specific Interrupt Numbers *******************************************************/ - WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ - WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ - WAKEUP2_IRQn = 2, - WAKEUP3_IRQn = 3, - WAKEUP4_IRQn = 4, - WAKEUP5_IRQn = 5, - WAKEUP6_IRQn = 6, - WAKEUP7_IRQn = 7, - WAKEUP8_IRQn = 8, - WAKEUP9_IRQn = 9, - WAKEUP10_IRQn = 10, - WAKEUP11_IRQn = 11, - WAKEUP12_IRQn = 12, - WAKEUP13_IRQn = 13, - WAKEUP14_IRQn = 14, - WAKEUP15_IRQn = 15, - WAKEUP16_IRQn = 16, - WAKEUP17_IRQn = 17, - WAKEUP18_IRQn = 18, - WAKEUP19_IRQn = 19, - WAKEUP20_IRQn = 20, - WAKEUP21_IRQn = 21, - WAKEUP22_IRQn = 22, - WAKEUP23_IRQn = 23, - WAKEUP24_IRQn = 24, - WAKEUP25_IRQn = 25, - WAKEUP26_IRQn = 26, - WAKEUP27_IRQn = 27, - WAKEUP28_IRQn = 28, - WAKEUP29_IRQn = 29, - WAKEUP30_IRQn = 30, - WAKEUP31_IRQn = 31, - WAKEUP32_IRQn = 32, - WAKEUP33_IRQn = 33, - WAKEUP34_IRQn = 34, - WAKEUP35_IRQn = 35, - WAKEUP36_IRQn = 36, - WAKEUP37_IRQn = 37, - WAKEUP38_IRQn = 38, - WAKEUP39_IRQn = 39, - I2C_IRQn = 40, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ - SSP_IRQn = 45, /*!< SSP Interrupt */ - UART_IRQn = 46, /*!< UART Interrupt */ - USB_IRQn = 47, /*!< USB Regular Interrupt */ - USB_FIQn = 48, /*!< USB Fast Interrupt */ - ADC_IRQn = 49, /*!< A/D Converter Interrupt */ - WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ - EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ - EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ - EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ - EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_LPC13xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ - __IO uint32_t PRESETCTRL; - __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ - __IO uint32_t SYSPLLSTAT; - __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ - __IO uint32_t USBPLLSTAT; - uint32_t RESERVED0[2]; - - __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ - __IO uint32_t WDTOSCCTRL; - __IO uint32_t IRCCTRL; - uint32_t RESERVED1[1]; - __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ - __IO uint32_t SYSPLLCLKUEN; - __IO uint32_t USBPLLCLKSEL; - __IO uint32_t USBPLLCLKUEN; - uint32_t RESERVED3[8]; - - __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ - __IO uint32_t MAINCLKUEN; - __IO uint32_t SYSAHBCLKDIV; - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ - uint32_t RESERVED5[4]; - __IO uint32_t SSPCLKDIV; - __IO uint32_t UARTCLKDIV; - uint32_t RESERVED6[4]; - __IO uint32_t TRACECLKDIV; - - __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ - uint32_t RESERVED7[3]; - - __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ - __IO uint32_t USBCLKUEN; - __IO uint32_t USBCLKDIV; - uint32_t RESERVED8[1]; - __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ - __IO uint32_t WDTCLKUEN; - __IO uint32_t WDTCLKDIV; - uint32_t RESERVED9[1]; - __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ - __IO uint32_t CLKOUTUEN; - __IO uint32_t CLKOUTDIV; - uint32_t RESERVED10[5]; - - __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ - __IO uint32_t PIOPORCAP1; - uint32_t RESERVED11[18]; - - __IO uint32_t BODCTRL; /* Offset 0x150 */ - uint32_t RESERVED12[1]; - __IO uint32_t SYSTCKCAL; - uint32_t RESERVED13[41]; - - __IO uint32_t STARTAPRP0; /* Offset 0x200 */ - __IO uint32_t STARTERP0; - __IO uint32_t STARTRSRP0CLR; - __IO uint32_t STARTSRP0; - __IO uint32_t STARTAPRP1; - __IO uint32_t STARTERP1; - __IO uint32_t STARTRSRP1CLR; - __IO uint32_t STARTSRP1; - uint32_t RESERVED14[4]; - - __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ - __IO uint32_t PDAWAKECFG; - __IO uint32_t PDRUNCFG; - uint32_t RESERVED15[110]; - __I uint32_t DEVICE_ID; -} LPC_SYSCON_TypeDef; - - -/*------------- Pin Connect Block (IOCON) --------------------------------*/ -typedef struct -{ - __IO uint32_t PIO2_6; - uint32_t RESERVED0[1]; - __IO uint32_t PIO2_0; - __IO uint32_t RESET_PIO0_0; - __IO uint32_t PIO0_1; - __IO uint32_t PIO1_8; - uint32_t RESERVED1[1]; - __IO uint32_t PIO0_2; - - __IO uint32_t PIO2_7; - __IO uint32_t PIO2_8; - __IO uint32_t PIO2_1; - __IO uint32_t PIO0_3; - __IO uint32_t PIO0_4; - __IO uint32_t PIO0_5; - __IO uint32_t PIO1_9; - __IO uint32_t PIO3_4; - - __IO uint32_t PIO2_4; - __IO uint32_t PIO2_5; - __IO uint32_t PIO3_5; - __IO uint32_t PIO0_6; - __IO uint32_t PIO0_7; - __IO uint32_t PIO2_9; - __IO uint32_t PIO2_10; - __IO uint32_t PIO2_2; - - __IO uint32_t PIO0_8; - __IO uint32_t PIO0_9; - __IO uint32_t JTAG_TCK_PIO0_10; - __IO uint32_t PIO1_10; - __IO uint32_t PIO2_11; - __IO uint32_t JTAG_TDI_PIO0_11; - __IO uint32_t JTAG_TMS_PIO1_0; - __IO uint32_t JTAG_TDO_PIO1_1; - - __IO uint32_t JTAG_nTRST_PIO1_2; - __IO uint32_t PIO3_0; - __IO uint32_t PIO3_1; - __IO uint32_t PIO2_3; - __IO uint32_t ARM_SWDIO_PIO1_3; - __IO uint32_t PIO1_4; - __IO uint32_t PIO1_11; - __IO uint32_t PIO3_2; - - __IO uint32_t PIO1_5; - __IO uint32_t PIO1_6; - __IO uint32_t PIO1_7; - __IO uint32_t PIO3_3; - __IO uint32_t SCKLOC; /* For HB1 only, new feature */ -} LPC_IOCON_TypeDef; - - -/*------------- Power Management Unit (PMU) --------------------------*/ -typedef struct -{ - __IO uint32_t PCON; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; -} LPC_PMU_TypeDef; - - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[4096]; - struct { - uint32_t RESERVED0[4095]; - __IO uint32_t DATA; - }; - }; - uint32_t RESERVED1[4096]; - __IO uint32_t DIR; - __IO uint32_t IS; - __IO uint32_t IBE; - __IO uint32_t IEV; - __IO uint32_t IE; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t IC; -} LPC_GPIO_TypeDef; - - -/*------------- Timer (TMR) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - uint32_t RESERVED1[3]; - __IO uint32_t EMR; - uint32_t RESERVED2[12]; - __IO uint32_t CTCR; - __IO uint32_t PWMC; -} LPC_TMR_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint32_t RBR; - __O uint32_t THR; - __IO uint32_t DLL; - }; - union { - __IO uint32_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint32_t FCR; - }; - __IO uint32_t LCR; - __IO uint32_t MCR; - __I uint32_t LSR; - __I uint32_t MSR; - __IO uint32_t SCR; - __IO uint32_t ACR; - __IO uint32_t ICR; - __IO uint32_t FDR; - uint32_t RESERVED0; - __IO uint32_t TER; - uint32_t RESERVED1[6]; - __IO uint32_t RS485CTRL; - __IO uint32_t ADRMATCH; - __IO uint32_t RS485DLY; - __I uint32_t FIFOLVL; -} LPC_UART_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; - __I uint32_t STAT; - __IO uint32_t DAT; - __IO uint32_t ADR0; - __IO uint32_t SCLH; - __IO uint32_t SCLL; - __O uint32_t CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t ADR1; - __IO uint32_t ADR2; - __IO uint32_t ADR3; - __I uint32_t DATA_BUFFER; - __IO uint32_t MASK0; - __IO uint32_t MASK1; - __IO uint32_t MASK2; - __IO uint32_t MASK3; -} LPC_I2C_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MOD; - __IO uint32_t TC; - __O uint32_t FEED; - __I uint32_t TV; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t GDR; - uint32_t RESERVED0; - __IO uint32_t INTEN; - __I uint32_t DR0; - __I uint32_t DR1; - __I uint32_t DR2; - __I uint32_t DR3; - __I uint32_t DR4; - __I uint32_t DR5; - __I uint32_t DR6; - __I uint32_t DR7; - __I uint32_t STAT; -} LPC_ADC_TypeDef; - - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevFIQSel; -} LPC_USB_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) - -/* AHB peripherals */ -#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) -#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) -#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) -#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) -#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) - -#endif // __LPC13xx_H__ +/**************************************************************************//** + * @file LPC13xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC13xx_H__ +#define __LPC13xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC13xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + WAKEUP13_IRQn = 13, + WAKEUP14_IRQn = 14, + WAKEUP15_IRQn = 15, + WAKEUP16_IRQn = 16, + WAKEUP17_IRQn = 17, + WAKEUP18_IRQn = 18, + WAKEUP19_IRQn = 19, + WAKEUP20_IRQn = 20, + WAKEUP21_IRQn = 21, + WAKEUP22_IRQn = 22, + WAKEUP23_IRQn = 23, + WAKEUP24_IRQn = 24, + WAKEUP25_IRQn = 25, + WAKEUP26_IRQn = 26, + WAKEUP27_IRQn = 27, + WAKEUP28_IRQn = 28, + WAKEUP29_IRQn = 29, + WAKEUP30_IRQn = 30, + WAKEUP31_IRQn = 31, + WAKEUP32_IRQn = 32, + WAKEUP33_IRQn = 33, + WAKEUP34_IRQn = 34, + WAKEUP35_IRQn = 35, + WAKEUP36_IRQn = 36, + WAKEUP37_IRQn = 37, + WAKEUP38_IRQn = 38, + WAKEUP39_IRQn = 39, + I2C_IRQn = 40, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ + SSP_IRQn = 45, /*!< SSP Interrupt */ + UART_IRQn = 46, /*!< UART Interrupt */ + USB_IRQn = 47, /*!< USB Regular Interrupt */ + USB_FIQn = 48, /*!< USB Fast Interrupt */ + ADC_IRQn = 49, /*!< A/D Converter Interrupt */ + WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ + EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC13xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ + __IO uint32_t PRESETCTRL; + __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ + __IO uint32_t SYSPLLSTAT; + __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ + __IO uint32_t USBPLLSTAT; + uint32_t RESERVED0[2]; + + __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ + __IO uint32_t WDTOSCCTRL; + __IO uint32_t IRCCTRL; + uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ + __IO uint32_t SYSPLLCLKUEN; + __IO uint32_t USBPLLCLKSEL; + __IO uint32_t USBPLLCLKUEN; + uint32_t RESERVED3[8]; + + __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ + __IO uint32_t MAINCLKUEN; + __IO uint32_t SYSAHBCLKDIV; + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ + uint32_t RESERVED5[4]; + __IO uint32_t SSPCLKDIV; + __IO uint32_t UARTCLKDIV; + uint32_t RESERVED6[4]; + __IO uint32_t TRACECLKDIV; + + __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ + uint32_t RESERVED7[3]; + + __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ + __IO uint32_t USBCLKUEN; + __IO uint32_t USBCLKDIV; + uint32_t RESERVED8[1]; + __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ + __IO uint32_t WDTCLKUEN; + __IO uint32_t WDTCLKDIV; + uint32_t RESERVED9[1]; + __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ + __IO uint32_t CLKOUTUEN; + __IO uint32_t CLKOUTDIV; + uint32_t RESERVED10[5]; + + __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ + __IO uint32_t PIOPORCAP1; + uint32_t RESERVED11[18]; + + __IO uint32_t BODCTRL; /* Offset 0x150 */ + uint32_t RESERVED12[1]; + __IO uint32_t SYSTCKCAL; + uint32_t RESERVED13[41]; + + __IO uint32_t STARTAPRP0; /* Offset 0x200 */ + __IO uint32_t STARTERP0; + __IO uint32_t STARTRSRP0CLR; + __IO uint32_t STARTSRP0; + __IO uint32_t STARTAPRP1; + __IO uint32_t STARTERP1; + __IO uint32_t STARTRSRP1CLR; + __IO uint32_t STARTSRP1; + uint32_t RESERVED14[4]; + + __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ + __IO uint32_t PDAWAKECFG; + __IO uint32_t PDRUNCFG; + uint32_t RESERVED15[110]; + __I uint32_t DEVICE_ID; +} LPC_SYSCON_TypeDef; + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +typedef struct +{ + __IO uint32_t PIO2_6; + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; + __IO uint32_t RESET_PIO0_0; + __IO uint32_t PIO0_1; + __IO uint32_t PIO1_8; + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; + + __IO uint32_t PIO2_7; + __IO uint32_t PIO2_8; + __IO uint32_t PIO2_1; + __IO uint32_t PIO0_3; + __IO uint32_t PIO0_4; + __IO uint32_t PIO0_5; + __IO uint32_t PIO1_9; + __IO uint32_t PIO3_4; + + __IO uint32_t PIO2_4; + __IO uint32_t PIO2_5; + __IO uint32_t PIO3_5; + __IO uint32_t PIO0_6; + __IO uint32_t PIO0_7; + __IO uint32_t PIO2_9; + __IO uint32_t PIO2_10; + __IO uint32_t PIO2_2; + + __IO uint32_t PIO0_8; + __IO uint32_t PIO0_9; + __IO uint32_t JTAG_TCK_PIO0_10; + __IO uint32_t PIO1_10; + __IO uint32_t PIO2_11; + __IO uint32_t JTAG_TDI_PIO0_11; + __IO uint32_t JTAG_TMS_PIO1_0; + __IO uint32_t JTAG_TDO_PIO1_1; + + __IO uint32_t JTAG_nTRST_PIO1_2; + __IO uint32_t PIO3_0; + __IO uint32_t PIO3_1; + __IO uint32_t PIO2_3; + __IO uint32_t ARM_SWDIO_PIO1_3; + __IO uint32_t PIO1_4; + __IO uint32_t PIO1_11; + __IO uint32_t PIO3_2; + + __IO uint32_t PIO1_5; + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO3_3; + __IO uint32_t SCKLOC; /* For HB1 only, new feature */ +} LPC_IOCON_TypeDef; + + +/*------------- Power Management Unit (PMU) --------------------------*/ +typedef struct +{ + __IO uint32_t PCON; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; +} LPC_PMU_TypeDef; + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; + __IO uint32_t IS; + __IO uint32_t IBE; + __IO uint32_t IEV; + __IO uint32_t IE; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t IC; +} LPC_GPIO_TypeDef; + + +/*------------- Timer (TMR) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + uint32_t RESERVED1[3]; + __IO uint32_t EMR; + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; + __IO uint32_t PWMC; +} LPC_TMR_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint32_t RBR; + __O uint32_t THR; + __IO uint32_t DLL; + }; + union { + __IO uint32_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint32_t FCR; + }; + __IO uint32_t LCR; + __IO uint32_t MCR; + __I uint32_t LSR; + __I uint32_t MSR; + __IO uint32_t SCR; + __IO uint32_t ACR; + __IO uint32_t ICR; + __IO uint32_t FDR; + uint32_t RESERVED0; + __IO uint32_t TER; + uint32_t RESERVED1[6]; + __IO uint32_t RS485CTRL; + __IO uint32_t ADRMATCH; + __IO uint32_t RS485DLY; + __I uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t CONSET; + __I uint32_t STAT; + __IO uint32_t DAT; + __IO uint32_t ADR0; + __IO uint32_t SCLH; + __IO uint32_t SCLL; + __O uint32_t CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t ADR1; + __IO uint32_t ADR2; + __IO uint32_t ADR3; + __I uint32_t DATA_BUFFER; + __IO uint32_t MASK0; + __IO uint32_t MASK1; + __IO uint32_t MASK2; + __IO uint32_t MASK3; +} LPC_I2C_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t TC; + __O uint32_t FEED; + __I uint32_t TV; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t GDR; + uint32_t RESERVED0; + __IO uint32_t INTEN; + __I uint32_t DR0; + __I uint32_t DR1; + __I uint32_t DR2; + __I uint32_t DR3; + __I uint32_t DR4; + __I uint32_t DR5; + __I uint32_t DR6; + __I uint32_t DR7; + __I uint32_t STAT; +} LPC_ADC_TypeDef; + + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t DevIntEn; + __O uint32_t DevIntClr; + __O uint32_t DevIntSet; + + __O uint32_t CmdCode; /* USB Device SIE Command Registers */ + __I uint32_t CmdData; + + __I uint32_t RxData; /* USB Device Transfer Registers */ + __O uint32_t TxData; + __I uint32_t RxPLen; + __O uint32_t TxPLen; + __IO uint32_t Ctrl; + __O uint32_t DevFIQSel; +} LPC_USB_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#endif // __LPC13xx_H__ diff --git a/firmware/CMSISv1p30_LPC13xx/inc/core_cm3.h b/firmware/CMSISv1p30_LPC13xx/inc/core_cm3.h index 2b6b51a..7ab7b4b 100644 --- a/firmware/CMSISv1p30_LPC13xx/inc/core_cm3.h +++ b/firmware/CMSISv1p30_LPC13xx/inc/core_cm3.h @@ -1,1818 +1,1818 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/firmware/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h b/firmware/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h index 5b9f2ff..1cb04fa 100644 --- a/firmware/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h +++ b/firmware/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h @@ -1,64 +1,64 @@ -/**************************************************************************//** - * @file system_LPC13xx.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC13xx Device Series - * @version V1.01 - * @date 19. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC13xx_H -#define __SYSTEM_LPC13xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC13x_H */ +/**************************************************************************//** + * @file system_LPC13xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC13xx_H +#define __SYSTEM_LPC13xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC13x_H */ diff --git a/firmware/CMSISv1p30_LPC13xx/src/core_cm3.c b/firmware/CMSISv1p30_LPC13xx/src/core_cm3.c index 56fddc5..fcff0d1 100644 --- a/firmware/CMSISv1p30_LPC13xx/src/core_cm3.c +++ b/firmware/CMSISv1p30_LPC13xx/src/core_cm3.c @@ -1,784 +1,784 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/firmware/CMSISv1p30_LPC13xx/src/system_LPC13xx.c b/firmware/CMSISv1p30_LPC13xx/src/system_LPC13xx.c index 3caaf6b..fec287a 100644 --- a/firmware/CMSISv1p30_LPC13xx/src/system_LPC13xx.c +++ b/firmware/CMSISv1p30_LPC13xx/src/system_LPC13xx.c @@ -1,487 +1,487 @@ -/**************************************************************************//** - * @file system_LPC13xx.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC13xx Device Series - * @version V1.02 - * @date 18. February 2010 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -// ******** Code Red ************** -// * Changed USBCLK_SETUP to 1 -// * Changed SYSPLLCTRL_Val to 0x25 -// ******************************** - -#include -#include "LPC13xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Clock Setup -// System Oscillator Enable -// Select System Oscillator Frequency Range -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -// Watchdog Oscillator Enable -// Select Divider for Fclkana -// <0=> 2 <1=> 4 <2=> 6 <3=> 8 -// <4=> 10 <5=> 12 <6=> 14 <7=> 16 -// <8=> 18 <9=> 20 <10=> 22 <11=> 24 -// <12=> 26 <13=> 28 <14=> 30 <15=> 32 -// <16=> 34 <17=> 36 <18=> 38 <19=> 40 -// <20=> 42 <21=> 44 <22=> 46 <23=> 48 -// <24=> 50 <25=> 52 <26=> 54 <27=> 56 -// <28=> 58 <29=> 60 <30=> 62 <31=> 64 -// Select Watchdog Oscillator Analog Frequency (Fclkana) -// <0=> Disabled -// <1=> 0.5 MHz -// <2=> 0.8 MHz -// <3=> 1.1 MHz -// <4=> 1.4 MHz -// <5=> 1.6 MHz -// <6=> 1.8 MHz -// <7=> 2.0 MHz -// <8=> 2.2 MHz -// <9=> 2.4 MHz -// <10=> 2.6 MHz -// <11=> 2.7 MHz -// <12=> 2.9 MHz -// <13=> 3.1 MHz -// <14=> 3.2 MHz -// <15=> 3.4 MHz -// -// Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL) -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> WDT Oscillator -// <3=> Invalid -// Use System PLL -// F_pll = M * F_in -// F_in must be in the range of 10 MHz to 25 MHz -// M: PLL Multiplier Selection -// <1-32><#-1> -// P: PLL Divider Selection -// <0=> 2 -// <1=> 4 -// <2=> 8 -// <3=> 16 -// DIRECT: Direct CCO Clock Output Enable -// BYPASS: PLL Bypass Enable -// -// Select Input Clock for Main clock (Register: MAINCLKSEL) -// <0=> IRC Oscillator -// <1=> Input Clock to System PLL -// <2=> WDT Oscillator -// <3=> System PLL Clock Out -// -// USB Clock Setup -// Use USB PLL -// F_pll = M * F_in -// F_in must be in the range of 10 MHz to 25 MHz -// Select Input Clock for usb_pllclkin (Register: USBPLLCLKSEL) -// <0=> IRC Oscillator -// <1=> System Oscillator -// M: PLL Multiplier Selection -// <1-32><#-1> -// P: PLL Divider Selection -// <0=> 2 -// <1=> 4 -// <2=> 8 -// <3=> 16 -// DIRECT: Direct CCO Clock Output Enable -// BYPASS: PLL Bypass Enable -// -// -// System AHB Divider <0-255> -// 0 = is disabled -// SYS Clock Enable -// ROM Clock Enable -// RAM Clock Enable -// FLASH1 Clock Enable -// FLASH2 Clock Enable -// I2C Clock Enable -// GPIO Clock Enable -// CT16B0 Clock Enable -// CT16B1 Clock Enable -// CT32B0 Clock Enable -// CT32B1 Clock Enable -// SSP Clock Enable -// UART Clock Enable -// ADC Clock Enable -// USB_REG Clock Enable -// SWDT Clock Enable -// IOCON Clock Enable -// -*/ -#define CLOCK_SETUP 1 -#define SYSCLK_SETUP 1 -#define SYSOSC_SETUP 1 -#define SYSOSCCTRL_Val 0x00000000 -#define WDTOSC_SETUP 0 -#define WDTOSCCTRL_Val 0x000000A0 -#define SYSPLLCLKSEL_Val 0x00000001 -#define SYSPLL_SETUP 1 -#define SYSPLLCTRL_Val 0x00000025 -#define MAINCLKSEL_Val 0x00000003 - -// ******** Code Red ********* -// * Changed USBCLK_SETUP to 1 -// *************************** -#define USBCLK_SETUP 1 -#define USBPLL_SETUP 1 -#define USBPLLCLKSEL_Val 0x00000001 -#define USBPLLCTRL_Val 0x00000003 -#define SYSAHBCLKDIV_Val 0x00000001 -#define AHBCLKCTRL_Val 0x0001005F - -/*--------------------- Memory Mapping Configuration ------------------------- -// -// Memory Mapping -// System Memory Remap (Register: SYSMEMREMAP) -// <0=> Bootloader mapped to address 0 -// <1=> RAM mapped to address 0 -// <2=> Flash mapped to address 0 -// <3=> Flash mapped to address 0 -// -*/ -#define MEMMAP_SETUP 0 -#define SYSMEMREMAP_Val 0x00000001 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) - #error "USBPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF)) - #error "USBPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((USBPLLUEN_Val), ~0x00000001)) - #error "USBPLLUEN: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - -#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF)) - #error "AHBCLKCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003)) - #error "SYSMEMREMAP: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (SYSCLK_SETUP) /* System Clock Setup */ - #if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 400000 / __DIVSEL) - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - #else - #define __WDT_OSC_CLK (1600000 / 2) - #endif // WDTOSC_SETUP - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 2) - #define __SYS_PLLCLKIN (__WDT_OSC_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #if (SYSPLL_SETUP) /* System PLL Setup */ - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - #else - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1)) - #endif // SYSPLL_SETUP - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - - #else // SYSCLK_SETUP - #if (SYSAHBCLKDIV_Val == 0) - #define __SYSTEM_CLOCK (0) - #else - #define __SYSTEM_CLOCK (__XTAL / SYSAHBCLKDIV_Val) - #endif - #endif // SYSCLK_SETUP - -#else - #define __SYSTEM_CLOCK (__XTAL) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 400000; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; - break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; - break; - case 3: /* Reserved */ - SystemCoreClock = 0; - break; - } - break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __IRC_OSC_CLK; - } else { - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 1: /* System oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __SYS_OSC_CLK; - } else { - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 2: /* WDT Oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = wdt_osc; - } else { - SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 3: /* Reserved */ - SystemCoreClock = 0; - break; - } - break; - } - - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#if (CLOCK_SETUP) /* Clock Setup */ -#if (SYSCLK_SETUP) /* System Clock Setup */ -#if (SYSOSC_SETUP) /* System Oscillator Setup */ - uint32_t i; - - LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */ - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; - for (i = 0; i < 200; i++) __NOP(); - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ -#if (SYSPLL_SETUP) /* System PLL Setup */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif -#endif -#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/ - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ -#endif - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ - LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->MAINCLKUEN = 0x01; - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ -#endif - -#if (USBCLK_SETUP) /* USB Clock Setup */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ -#if (USBPLL_SETUP) /* USB PLL Setup */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ - LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->USBPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ - LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; - while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ - LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ -#else - LPC_SYSCON->USBCLKSEL = 0x01; /* Select Main Clock */ -#endif -#else - LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ - LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ -#endif - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; - LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val; -#endif - - -#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */ - LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val; -#endif -} +/**************************************************************************//** + * @file system_LPC13xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the NXP LPC13xx Device Series + * @version V1.02 + * @date 18. February 2010 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// ******** Code Red ************** +// * Changed USBCLK_SETUP to 1 +// * Changed SYSPLLCTRL_Val to 0x25 +// ******************************** + +#include +#include "LPC13xx.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Clock Setup +// System Oscillator Enable +// Select System Oscillator Frequency Range +// <0=> 1 - 20 MHz +// <1=> 15 - 25 MHz +// +// Watchdog Oscillator Enable +// Select Divider for Fclkana +// <0=> 2 <1=> 4 <2=> 6 <3=> 8 +// <4=> 10 <5=> 12 <6=> 14 <7=> 16 +// <8=> 18 <9=> 20 <10=> 22 <11=> 24 +// <12=> 26 <13=> 28 <14=> 30 <15=> 32 +// <16=> 34 <17=> 36 <18=> 38 <19=> 40 +// <20=> 42 <21=> 44 <22=> 46 <23=> 48 +// <24=> 50 <25=> 52 <26=> 54 <27=> 56 +// <28=> 58 <29=> 60 <30=> 62 <31=> 64 +// Select Watchdog Oscillator Analog Frequency (Fclkana) +// <0=> Disabled +// <1=> 0.5 MHz +// <2=> 0.8 MHz +// <3=> 1.1 MHz +// <4=> 1.4 MHz +// <5=> 1.6 MHz +// <6=> 1.8 MHz +// <7=> 2.0 MHz +// <8=> 2.2 MHz +// <9=> 2.4 MHz +// <10=> 2.6 MHz +// <11=> 2.7 MHz +// <12=> 2.9 MHz +// <13=> 3.1 MHz +// <14=> 3.2 MHz +// <15=> 3.4 MHz +// +// Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL) +// <0=> IRC Oscillator +// <1=> System Oscillator +// <2=> WDT Oscillator +// <3=> Invalid +// Use System PLL +// F_pll = M * F_in +// F_in must be in the range of 10 MHz to 25 MHz +// M: PLL Multiplier Selection +// <1-32><#-1> +// P: PLL Divider Selection +// <0=> 2 +// <1=> 4 +// <2=> 8 +// <3=> 16 +// DIRECT: Direct CCO Clock Output Enable +// BYPASS: PLL Bypass Enable +// +// Select Input Clock for Main clock (Register: MAINCLKSEL) +// <0=> IRC Oscillator +// <1=> Input Clock to System PLL +// <2=> WDT Oscillator +// <3=> System PLL Clock Out +// +// USB Clock Setup +// Use USB PLL +// F_pll = M * F_in +// F_in must be in the range of 10 MHz to 25 MHz +// Select Input Clock for usb_pllclkin (Register: USBPLLCLKSEL) +// <0=> IRC Oscillator +// <1=> System Oscillator +// M: PLL Multiplier Selection +// <1-32><#-1> +// P: PLL Divider Selection +// <0=> 2 +// <1=> 4 +// <2=> 8 +// <3=> 16 +// DIRECT: Direct CCO Clock Output Enable +// BYPASS: PLL Bypass Enable +// +// +// System AHB Divider <0-255> +// 0 = is disabled +// SYS Clock Enable +// ROM Clock Enable +// RAM Clock Enable +// FLASH1 Clock Enable +// FLASH2 Clock Enable +// I2C Clock Enable +// GPIO Clock Enable +// CT16B0 Clock Enable +// CT16B1 Clock Enable +// CT32B0 Clock Enable +// CT32B1 Clock Enable +// SSP Clock Enable +// UART Clock Enable +// ADC Clock Enable +// USB_REG Clock Enable +// SWDT Clock Enable +// IOCON Clock Enable +// +*/ +#define CLOCK_SETUP 1 +#define SYSCLK_SETUP 1 +#define SYSOSC_SETUP 1 +#define SYSOSCCTRL_Val 0x00000000 +#define WDTOSC_SETUP 0 +#define WDTOSCCTRL_Val 0x000000A0 +#define SYSPLLCLKSEL_Val 0x00000001 +#define SYSPLL_SETUP 1 +#define SYSPLLCTRL_Val 0x00000025 +#define MAINCLKSEL_Val 0x00000003 + +// ******** Code Red ********* +// * Changed USBCLK_SETUP to 1 +// *************************** +#define USBCLK_SETUP 1 +#define USBPLL_SETUP 1 +#define USBPLLCLKSEL_Val 0x00000001 +#define USBPLLCTRL_Val 0x00000003 +#define SYSAHBCLKDIV_Val 0x00000001 +#define AHBCLKCTRL_Val 0x0001005F + +/*--------------------- Memory Mapping Configuration ------------------------- +// +// Memory Mapping +// System Memory Remap (Register: SYSMEMREMAP) +// <0=> Bootloader mapped to address 0 +// <1=> RAM mapped to address 0 +// <2=> Flash mapped to address 0 +// <3=> Flash mapped to address 0 +// +*/ +#define MEMMAP_SETUP 0 +#define SYSMEMREMAP_Val 0x00000001 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) + #error "SYSOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) + #error "WDTOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) + #error "SYSPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) + #error "SYSPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) + #error "MAINCLKSEL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) + #error "USBPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF)) + #error "USBPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((USBPLLUEN_Val), ~0x00000001)) + #error "USBPLLUEN: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) + #error "SYSAHBCLKDIV: Value out of range!" +#endif + +#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF)) + #error "AHBCLKCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003)) + #error "SYSMEMREMAP: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (12000000UL) /* Oscillator frequency */ +#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ +#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ + + +#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) +#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) + +#if (CLOCK_SETUP) /* Clock Setup */ + #if (SYSCLK_SETUP) /* System Clock Setup */ + #if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/ + #if (__FREQSEL == 0) + #define __WDT_OSC_CLK ( 400000 / __DIVSEL) + #elif (__FREQSEL == 1) + #define __WDT_OSC_CLK ( 500000 / __DIVSEL) + #elif (__FREQSEL == 2) + #define __WDT_OSC_CLK ( 800000 / __DIVSEL) + #elif (__FREQSEL == 3) + #define __WDT_OSC_CLK (1100000 / __DIVSEL) + #elif (__FREQSEL == 4) + #define __WDT_OSC_CLK (1400000 / __DIVSEL) + #elif (__FREQSEL == 5) + #define __WDT_OSC_CLK (1600000 / __DIVSEL) + #elif (__FREQSEL == 6) + #define __WDT_OSC_CLK (1800000 / __DIVSEL) + #elif (__FREQSEL == 7) + #define __WDT_OSC_CLK (2000000 / __DIVSEL) + #elif (__FREQSEL == 8) + #define __WDT_OSC_CLK (2200000 / __DIVSEL) + #elif (__FREQSEL == 9) + #define __WDT_OSC_CLK (2400000 / __DIVSEL) + #elif (__FREQSEL == 10) + #define __WDT_OSC_CLK (2600000 / __DIVSEL) + #elif (__FREQSEL == 11) + #define __WDT_OSC_CLK (2700000 / __DIVSEL) + #elif (__FREQSEL == 12) + #define __WDT_OSC_CLK (2900000 / __DIVSEL) + #elif (__FREQSEL == 13) + #define __WDT_OSC_CLK (3100000 / __DIVSEL) + #elif (__FREQSEL == 14) + #define __WDT_OSC_CLK (3200000 / __DIVSEL) + #else + #define __WDT_OSC_CLK (3400000 / __DIVSEL) + #endif + #else + #define __WDT_OSC_CLK (1600000 / 2) + #endif // WDTOSC_SETUP + + /* sys_pllclkin calculation */ + #if ((SYSPLLCLKSEL_Val & 0x03) == 0) + #define __SYS_PLLCLKIN (__IRC_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) + #define __SYS_PLLCLKIN (__SYS_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 2) + #define __SYS_PLLCLKIN (__WDT_OSC_CLK) + #else + #define __SYS_PLLCLKIN (0) + #endif + + #if (SYSPLL_SETUP) /* System PLL Setup */ + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) + #else + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1)) + #endif // SYSPLL_SETUP + + /* main clock calculation */ + #if ((MAINCLKSEL_Val & 0x03) == 0) + #define __MAIN_CLOCK (__IRC_OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 1) + #define __MAIN_CLOCK (__SYS_PLLCLKIN) + #elif ((MAINCLKSEL_Val & 0x03) == 2) + #define __MAIN_CLOCK (__WDT_OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 3) + #define __MAIN_CLOCK (__SYS_PLLCLKOUT) + #else + #define __MAIN_CLOCK (0) + #endif + + #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) + + #else // SYSCLK_SETUP + #if (SYSAHBCLKDIV_Val == 0) + #define __SYSTEM_CLOCK (0) + #else + #define __SYSTEM_CLOCK (__XTAL / SYSAHBCLKDIV_Val) + #endif + #endif // SYSCLK_SETUP + +#else + #define __SYSTEM_CLOCK (__XTAL) +#endif // CLOCK_SETUP + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t wdt_osc = 0; + + /* Determine clock frequency according to clock register values */ + switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { + case 0: wdt_osc = 400000; break; + case 1: wdt_osc = 500000; break; + case 2: wdt_osc = 800000; break; + case 3: wdt_osc = 1100000; break; + case 4: wdt_osc = 1400000; break; + case 5: wdt_osc = 1600000; break; + case 6: wdt_osc = 1800000; break; + case 7: wdt_osc = 2000000; break; + case 8: wdt_osc = 2200000; break; + case 9: wdt_osc = 2400000; break; + case 10: wdt_osc = 2600000; break; + case 11: wdt_osc = 2700000; break; + case 12: wdt_osc = 2900000; break; + case 13: wdt_osc = 3100000; break; + case 14: wdt_osc = 3200000; break; + case 15: wdt_osc = 3400000; break; + } + wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; + + switch (LPC_SYSCON->MAINCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* Input Clock to System PLL */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK; + break; + case 2: /* WDT Oscillator */ + SystemCoreClock = wdt_osc; + break; + case 3: /* Reserved */ + SystemCoreClock = 0; + break; + } + break; + case 2: /* WDT Oscillator */ + SystemCoreClock = wdt_osc; + break; + case 3: /* System PLL Clock Out */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = __IRC_OSC_CLK; + } else { + SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 1: /* System oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = __SYS_OSC_CLK; + } else { + SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 2: /* WDT Oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = wdt_osc; + } else { + SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 3: /* Reserved */ + SystemCoreClock = 0; + break; + } + break; + } + + SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (CLOCK_SETUP) /* Clock Setup */ +#if (SYSCLK_SETUP) /* System Clock Setup */ +#if (SYSOSC_SETUP) /* System Oscillator Setup */ + uint32_t i; + + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */ + LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; + for (i = 0; i < 200; i++) __NOP(); + LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ + LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ + LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->SYSPLLCLKUEN = 0x01; + while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ +#if (SYSPLL_SETUP) /* System PLL Setup */ + LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ + while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ +#endif +#endif +#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/ + LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ +#endif + LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ + LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ + LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->MAINCLKUEN = 0x01; + while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ +#endif + +#if (USBCLK_SETUP) /* USB Clock Setup */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ +#if (USBPLL_SETUP) /* USB PLL Setup */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ + LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ + LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ + LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->USBPLLCLKUEN = 0x01; + while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ + LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; + while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ + LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ +#else + LPC_SYSCON->USBCLKSEL = 0x01; /* Select Main Clock */ +#endif +#else + LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ + LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ +#endif + + LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; + LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val; +#endif + + +#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */ + LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val; +#endif +} diff --git a/firmware/usbcomp_msd_cdc/.cproject b/firmware/usbcomp_msd_cdc/.cproject index 5821523..9d5f2ff 100644 --- a/firmware/usbcomp_msd_cdc/.cproject +++ b/firmware/usbcomp_msd_cdc/.cproject @@ -1,1336 +1,1336 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - -<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1343" property_count="5" version="1"/> -<infoList vendor="NXP"> -<info chip="LPC1343" match_id="0x3d00002b" name="LPC1343" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC1343</name> -<family>LPC13xx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash32" location="0x00000000" size="0x8000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x8000"/> -<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> -<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> -<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> -<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> -<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP" location="0x40040000"/> -<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> -<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> -<peripheralInstance derived_from="LPC13_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> -<peripheralInstance derived_from="LPC11_13_PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="LPC11_13_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> -<peripheralInstance derived_from="LPC11_13_USBDEV" determined="infoFile" id="USB" location="0x40020000"/> -<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> -</chip> -<processor> -<name gcc_name="cortex-m3">Cortex-M3</name> -<family>Cortex-M</family> -</processor> -<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig> - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+<chip> +<name>LPC1343</name> +<family>LPC13xx</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash32" location="0x00000000" size="0x8000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x8000"/> +<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> +<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> +<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP" location="0x40040000"/> +<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> +<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> +<peripheralInstance derived_from="LPC13_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> +<peripheralInstance derived_from="LPC11_13_PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="LPC11_13_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> +<peripheralInstance derived_from="LPC11_13_USBDEV" determined="infoFile" id="USB" location="0x40020000"/> +<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> +</chip> +<processor> +<name gcc_name="cortex-m3">Cortex-M3</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + diff --git a/firmware/usbcomp_msd_cdc/.project b/firmware/usbcomp_msd_cdc/.project index d09c1ae..437f4b2 100644 --- a/firmware/usbcomp_msd_cdc/.project +++ b/firmware/usbcomp_msd_cdc/.project @@ -1,82 +1,82 @@ - - - usbcomp_msd_cdc - - - CMSISv1p30_LPC13xx - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/usbcomp_msd_cdc/Debug} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - + + + usbcomp_msd_cdc + + + CMSISv1p30_LPC13xx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/usbcomp_msd_cdc/Debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/firmware/usbcomp_msd_cdc/AN composite device.docx b/firmware/usbcomp_msd_cdc/AN composite device.docx deleted file mode 100644 index 06547ec..0000000 Binary files a/firmware/usbcomp_msd_cdc/AN composite device.docx and /dev/null differ diff --git a/firmware/usbcomp_msd_cdc/inc/cdc.h b/firmware/usbcomp_msd_cdc/inc/cdc.h index 358129c..f7af7d3 100644 --- a/firmware/usbcomp_msd_cdc/inc/cdc.h +++ b/firmware/usbcomp_msd_cdc/inc/cdc.h @@ -1,236 +1,236 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: CDC.h - * Purpose: USB Communication Device Class Definitions - * Version: V1.00 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __CDC_H -#define __CDC_H - -/*---------------------------------------------------------------------------- - * Definitions based on usbcdc11.pdf (www.usb.org) - *---------------------------------------------------------------------------*/ -// Communication device class specification version 1.10 -#define CDC_V1_10 0x0110 - -// Communication interface class code -// (usbcdc11.pdf, 4.2, Table 15) -#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02 - -// Communication interface class subclass codes -// (usbcdc11.pdf, 4.3, Table 16) -#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01 -#define CDC_ABSTRACT_CONTROL_MODEL 0x02 -#define CDC_TELEPHONE_CONTROL_MODEL 0x03 -#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04 -#define CDC_CAPI_CONTROL_MODEL 0x05 -#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06 -#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07 - -// Communication interface class control protocol codes -// (usbcdc11.pdf, 4.4, Table 17) -#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01 - -// Data interface class code -// (usbcdc11.pdf, 4.5, Table 18) -#define CDC_DATA_INTERFACE_CLASS 0x0A - -// Data interface class protocol codes -// (usbcdc11.pdf, 4.7, Table 19) -#define CDC_PROTOCOL_ISDN_BRI 0x30 -#define CDC_PROTOCOL_HDLC 0x31 -#define CDC_PROTOCOL_TRANSPARENT 0x32 -#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50 -#define CDC_PROTOCOL_Q921_DATA_LINK 0x51 -#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52 -#define CDC_PROTOCOL_V42 0x90 -#define CDC_PROTOCOL_EURO_ISDN 0x91 -#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92 -#define CDC_PROTOCOL_CAPI 0x93 -#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD -#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE - -// Type values for bDescriptorType field of functional descriptors -// (usbcdc11.pdf, 5.2.3, Table 24) -#define CDC_CS_INTERFACE 0x24 -#define CDC_CS_ENDPOINT 0x25 - -// Type values for bDescriptorSubtype field of functional descriptors -// (usbcdc11.pdf, 5.2.3, Table 25) -#define CDC_HEADER 0x00 -#define CDC_CALL_MANAGEMENT 0x01 -#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02 -#define CDC_DIRECT_LINE_MANAGEMENT 0x03 -#define CDC_TELEPHONE_RINGER 0x04 -#define CDC_REPORTING_CAPABILITIES 0x05 -#define CDC_UNION 0x06 -#define CDC_COUNTRY_SELECTION 0x07 -#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08 -#define CDC_USB_TERMINAL 0x09 -#define CDC_NETWORK_CHANNEL 0x0A -#define CDC_PROTOCOL_UNIT 0x0B -#define CDC_EXTENSION_UNIT 0x0C -#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D -#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E -#define CDC_ETHERNET_NETWORKING 0x0F -#define CDC_ATM_NETWORKING 0x10 - -// CDC class-specific request codes -// (usbcdc11.pdf, 6.2, Table 46) -// see Table 45 for info about the specific requests. -#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define CDC_SET_COMM_FEATURE 0x02 -#define CDC_GET_COMM_FEATURE 0x03 -#define CDC_CLEAR_COMM_FEATURE 0x04 -#define CDC_SET_AUX_LINE_STATE 0x10 -#define CDC_SET_HOOK_STATE 0x11 -#define CDC_PULSE_SETUP 0x12 -#define CDC_SEND_PULSE 0x13 -#define CDC_SET_PULSE_TIME 0x14 -#define CDC_RING_AUX_JACK 0x15 -#define CDC_SET_LINE_CODING 0x20 -#define CDC_GET_LINE_CODING 0x21 -#define CDC_SET_CONTROL_LINE_STATE 0x22 -#define CDC_SEND_BREAK 0x23 -#define CDC_SET_RINGER_PARMS 0x30 -#define CDC_GET_RINGER_PARMS 0x31 -#define CDC_SET_OPERATION_PARMS 0x32 -#define CDC_GET_OPERATION_PARMS 0x33 -#define CDC_SET_LINE_PARMS 0x34 -#define CDC_GET_LINE_PARMS 0x35 -#define CDC_DIAL_DIGITS 0x36 -#define CDC_SET_UNIT_PARAMETER 0x37 -#define CDC_GET_UNIT_PARAMETER 0x38 -#define CDC_CLEAR_UNIT_PARAMETER 0x39 -#define CDC_GET_PROFILE 0x3A -#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 -#define CDC_SET_ETHERNET_PMP_FILTER 0x41 -#define CDC_GET_ETHERNET_PMP_FILTER 0x42 -#define CDC_SET_ETHERNET_PACKET_FILTER 0x43 -#define CDC_GET_ETHERNET_STATISTIC 0x44 -#define CDC_SET_ATM_DATA_FORMAT 0x50 -#define CDC_GET_ATM_DEVICE_STATISTICS 0x51 -#define CDC_SET_ATM_DEFAULT_VC 0x52 -#define CDC_GET_ATM_VC_STATISTICS 0x53 - -// Communication feature selector codes -// (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) -#define CDC_ABSTRACT_STATE 0x01 -#define CDC_COUNTRY_SETTING 0x02 - -// Feature Status returned for ABSTRACT_STATE Selector -// (usbcdc11.pdf, 6.2.3, Table 48) -#define CDC_IDLE_SETTING (1 << 0) -#define CDC_DATA_MULTPLEXED_STATE (1 << 1) - - -// Control signal bitmap values for the SetControlLineState request -// (usbcdc11.pdf, 6.2.14, Table 51) -#define CDC_DTE_PRESENT (1 << 0) -#define CDC_ACTIVATE_CARRIER (1 << 1) - -// CDC class-specific notification codes -// (usbcdc11.pdf, 6.3, Table 68) -// see Table 67 for Info about class-specific notifications -#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 -#define CDC_RESPONSE_AVAILABLE 0x01 -#define CDC_AUX_JACK_HOOK_STATE 0x08 -#define CDC_RING_DETECT 0x09 -#define CDC_NOTIFICATION_SERIAL_STATE 0x20 -#define CDC_CALL_STATE_CHANGE 0x28 -#define CDC_LINE_STATE_CHANGE 0x29 -#define CDC_CONNECTION_SPEED_CHANGE 0x2A - -// UART state bitmap values (Serial state notification). -// (usbcdc11.pdf, 6.3.5, Table 69) -#define CDC_SERIAL_STATE_OVERRUN (1 << 6) // receive data overrun error has occurred -#define CDC_SERIAL_STATE_PARITY (1 << 5) // parity error has occurred -#define CDC_SERIAL_STATE_FRAMING (1 << 4) // framing error has occurred -#define CDC_SERIAL_STATE_RING (1 << 3) // state of ring signal detection -#define CDC_SERIAL_STATE_BREAK (1 << 2) // state of break detection -#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) // state of transmission carrier -#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) // state of receiver carrier - - -/*---------------------------------------------------------------------------- - * Structures based on usbcdc11.pdf (www.usb.org) - *---------------------------------------------------------------------------*/ - -// Header functional descriptor -// (usbcdc11.pdf, 5.2.3.1) -// This header must precede any list of class-specific descriptors. -typedef struct _CDC_HEADER_DESCRIPTOR{ - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // Header functional descriptor subtype - uint16_t bcdCDC; // USB CDC specification release version -} __attribute__((packed)) CDC_HEADER_DESCRIPTOR; - -//Call management functional descriptor -// (usbcdc11.pdf, 5.2.3.2) -// Describes the processing of calls for the communication class interface. -typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR { - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // call management functional descriptor subtype - uint8_t bmCapabilities; // capabilities that this configuration supports - uint8_t bDataInterface; // interface number of the data class interface used for call management (optional) -} __attribute__((packed)) CDC_CALL_MANAGEMENT_DESCRIPTOR; - -// Abstract control management functional descriptor -// (usbcdc11.pdf, 5.2.3.3) -// Describes the command supported by the communication interface class with the Abstract Control Model subclass code. -typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR { - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // abstract control management functional descriptor subtype - uint8_t bmCapabilities; // capabilities supported by this configuration -} __attribute__((packed)) CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR; - -// Union functional descriptors -// (usbcdc11.pdf, 5.2.3.8) -// Describes the relationship between a group of interfaces that can be considered to form a functional unit. -typedef struct _CDC_UNION_DESCRIPTOR { - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // union functional descriptor subtype - uint8_t bMasterInterface; // interface number designated as master -} __attribute__((packed)) CDC_UNION_DESCRIPTOR; - -// Union functional descriptors with one slave interface -// (usbcdc11.pdf, 5.2.3.8) -typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR { - CDC_UNION_DESCRIPTOR sUnion; // Union functional descriptor - uint8_t bSlaveInterfaces[1]; // Slave interface 0 -} __attribute__((packed)) CDC_UNION_1SLAVE_DESCRIPTOR; - -// Line coding structure -// Format of the data returned when a GetLineCoding request is received -// (usbcdc11.pdf, 6.2.13) -typedef struct _CDC_LINE_CODING { - uint32_t dwDTERate; // Data terminal rate in bits per second - uint8_t bCharFormat; // Number of stop bits - uint8_t bParityType; // Parity bit type - uint8_t bDataBits; // Number of data bits -} __attribute__((packed)) CDC_LINE_CODING; - -// Notification header -// Data sent on the notification endpoint must follow this header. -// see USB_SETUP_PACKET in file usb.h -typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER; - -#endif /* __CDC_H */ - +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: CDC.h + * Purpose: USB Communication Device Class Definitions + * Version: V1.00 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __CDC_H +#define __CDC_H + +/*---------------------------------------------------------------------------- + * Definitions based on usbcdc11.pdf (www.usb.org) + *---------------------------------------------------------------------------*/ +// Communication device class specification version 1.10 +#define CDC_V1_10 0x0110 + +// Communication interface class code +// (usbcdc11.pdf, 4.2, Table 15) +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02 + +// Communication interface class subclass codes +// (usbcdc11.pdf, 4.3, Table 16) +#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01 +#define CDC_ABSTRACT_CONTROL_MODEL 0x02 +#define CDC_TELEPHONE_CONTROL_MODEL 0x03 +#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04 +#define CDC_CAPI_CONTROL_MODEL 0x05 +#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06 +#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07 + +// Communication interface class control protocol codes +// (usbcdc11.pdf, 4.4, Table 17) +#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01 + +// Data interface class code +// (usbcdc11.pdf, 4.5, Table 18) +#define CDC_DATA_INTERFACE_CLASS 0x0A + +// Data interface class protocol codes +// (usbcdc11.pdf, 4.7, Table 19) +#define CDC_PROTOCOL_ISDN_BRI 0x30 +#define CDC_PROTOCOL_HDLC 0x31 +#define CDC_PROTOCOL_TRANSPARENT 0x32 +#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50 +#define CDC_PROTOCOL_Q921_DATA_LINK 0x51 +#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52 +#define CDC_PROTOCOL_V42 0x90 +#define CDC_PROTOCOL_EURO_ISDN 0x91 +#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92 +#define CDC_PROTOCOL_CAPI 0x93 +#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD +#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE + +// Type values for bDescriptorType field of functional descriptors +// (usbcdc11.pdf, 5.2.3, Table 24) +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + +// Type values for bDescriptorSubtype field of functional descriptors +// (usbcdc11.pdf, 5.2.3, Table 25) +#define CDC_HEADER 0x00 +#define CDC_CALL_MANAGEMENT 0x01 +#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_DIRECT_LINE_MANAGEMENT 0x03 +#define CDC_TELEPHONE_RINGER 0x04 +#define CDC_REPORTING_CAPABILITIES 0x05 +#define CDC_UNION 0x06 +#define CDC_COUNTRY_SELECTION 0x07 +#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08 +#define CDC_USB_TERMINAL 0x09 +#define CDC_NETWORK_CHANNEL 0x0A +#define CDC_PROTOCOL_UNIT 0x0B +#define CDC_EXTENSION_UNIT 0x0C +#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D +#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E +#define CDC_ETHERNET_NETWORKING 0x0F +#define CDC_ATM_NETWORKING 0x10 + +// CDC class-specific request codes +// (usbcdc11.pdf, 6.2, Table 46) +// see Table 45 for info about the specific requests. +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 +#define CDC_SET_AUX_LINE_STATE 0x10 +#define CDC_SET_HOOK_STATE 0x11 +#define CDC_PULSE_SETUP 0x12 +#define CDC_SEND_PULSE 0x13 +#define CDC_SET_PULSE_TIME 0x14 +#define CDC_RING_AUX_JACK 0x15 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 +#define CDC_SET_RINGER_PARMS 0x30 +#define CDC_GET_RINGER_PARMS 0x31 +#define CDC_SET_OPERATION_PARMS 0x32 +#define CDC_GET_OPERATION_PARMS 0x33 +#define CDC_SET_LINE_PARMS 0x34 +#define CDC_GET_LINE_PARMS 0x35 +#define CDC_DIAL_DIGITS 0x36 +#define CDC_SET_UNIT_PARAMETER 0x37 +#define CDC_GET_UNIT_PARAMETER 0x38 +#define CDC_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_GET_PROFILE 0x3A +#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_SET_ETHERNET_PMP_FILTER 0x41 +#define CDC_GET_ETHERNET_PMP_FILTER 0x42 +#define CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_GET_ETHERNET_STATISTIC 0x44 +#define CDC_SET_ATM_DATA_FORMAT 0x50 +#define CDC_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_SET_ATM_DEFAULT_VC 0x52 +#define CDC_GET_ATM_VC_STATISTICS 0x53 + +// Communication feature selector codes +// (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) +#define CDC_ABSTRACT_STATE 0x01 +#define CDC_COUNTRY_SETTING 0x02 + +// Feature Status returned for ABSTRACT_STATE Selector +// (usbcdc11.pdf, 6.2.3, Table 48) +#define CDC_IDLE_SETTING (1 << 0) +#define CDC_DATA_MULTPLEXED_STATE (1 << 1) + + +// Control signal bitmap values for the SetControlLineState request +// (usbcdc11.pdf, 6.2.14, Table 51) +#define CDC_DTE_PRESENT (1 << 0) +#define CDC_ACTIVATE_CARRIER (1 << 1) + +// CDC class-specific notification codes +// (usbcdc11.pdf, 6.3, Table 68) +// see Table 67 for Info about class-specific notifications +#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 +#define CDC_RESPONSE_AVAILABLE 0x01 +#define CDC_AUX_JACK_HOOK_STATE 0x08 +#define CDC_RING_DETECT 0x09 +#define CDC_NOTIFICATION_SERIAL_STATE 0x20 +#define CDC_CALL_STATE_CHANGE 0x28 +#define CDC_LINE_STATE_CHANGE 0x29 +#define CDC_CONNECTION_SPEED_CHANGE 0x2A + +// UART state bitmap values (Serial state notification). +// (usbcdc11.pdf, 6.3.5, Table 69) +#define CDC_SERIAL_STATE_OVERRUN (1 << 6) // receive data overrun error has occurred +#define CDC_SERIAL_STATE_PARITY (1 << 5) // parity error has occurred +#define CDC_SERIAL_STATE_FRAMING (1 << 4) // framing error has occurred +#define CDC_SERIAL_STATE_RING (1 << 3) // state of ring signal detection +#define CDC_SERIAL_STATE_BREAK (1 << 2) // state of break detection +#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) // state of transmission carrier +#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) // state of receiver carrier + + +/*---------------------------------------------------------------------------- + * Structures based on usbcdc11.pdf (www.usb.org) + *---------------------------------------------------------------------------*/ + +// Header functional descriptor +// (usbcdc11.pdf, 5.2.3.1) +// This header must precede any list of class-specific descriptors. +typedef struct _CDC_HEADER_DESCRIPTOR{ + uint8_t bFunctionLength; // size of this descriptor in bytes + uint8_t bDescriptorType; // CS_INTERFACE descriptor type + uint8_t bDescriptorSubtype; // Header functional descriptor subtype + uint16_t bcdCDC; // USB CDC specification release version +} __attribute__((packed)) CDC_HEADER_DESCRIPTOR; + +//Call management functional descriptor +// (usbcdc11.pdf, 5.2.3.2) +// Describes the processing of calls for the communication class interface. +typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR { + uint8_t bFunctionLength; // size of this descriptor in bytes + uint8_t bDescriptorType; // CS_INTERFACE descriptor type + uint8_t bDescriptorSubtype; // call management functional descriptor subtype + uint8_t bmCapabilities; // capabilities that this configuration supports + uint8_t bDataInterface; // interface number of the data class interface used for call management (optional) +} __attribute__((packed)) CDC_CALL_MANAGEMENT_DESCRIPTOR; + +// Abstract control management functional descriptor +// (usbcdc11.pdf, 5.2.3.3) +// Describes the command supported by the communication interface class with the Abstract Control Model subclass code. +typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR { + uint8_t bFunctionLength; // size of this descriptor in bytes + uint8_t bDescriptorType; // CS_INTERFACE descriptor type + uint8_t bDescriptorSubtype; // abstract control management functional descriptor subtype + uint8_t bmCapabilities; // capabilities supported by this configuration +} __attribute__((packed)) CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR; + +// Union functional descriptors +// (usbcdc11.pdf, 5.2.3.8) +// Describes the relationship between a group of interfaces that can be considered to form a functional unit. +typedef struct _CDC_UNION_DESCRIPTOR { + uint8_t bFunctionLength; // size of this descriptor in bytes + uint8_t bDescriptorType; // CS_INTERFACE descriptor type + uint8_t bDescriptorSubtype; // union functional descriptor subtype + uint8_t bMasterInterface; // interface number designated as master +} __attribute__((packed)) CDC_UNION_DESCRIPTOR; + +// Union functional descriptors with one slave interface +// (usbcdc11.pdf, 5.2.3.8) +typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR { + CDC_UNION_DESCRIPTOR sUnion; // Union functional descriptor + uint8_t bSlaveInterfaces[1]; // Slave interface 0 +} __attribute__((packed)) CDC_UNION_1SLAVE_DESCRIPTOR; + +// Line coding structure +// Format of the data returned when a GetLineCoding request is received +// (usbcdc11.pdf, 6.2.13) +typedef struct _CDC_LINE_CODING { + uint32_t dwDTERate; // Data terminal rate in bits per second + uint8_t bCharFormat; // Number of stop bits + uint8_t bParityType; // Parity bit type + uint8_t bDataBits; // Number of data bits +} __attribute__((packed)) CDC_LINE_CODING; + +// Notification header +// Data sent on the notification endpoint must follow this header. +// see USB_SETUP_PACKET in file usb.h +typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER; + +#endif /* __CDC_H */ + diff --git a/firmware/usbcomp_msd_cdc/inc/cdcuser.h b/firmware/usbcomp_msd_cdc/inc/cdcuser.h index 76f978f..7512157 100644 --- a/firmware/usbcomp_msd_cdc/inc/cdcuser.h +++ b/firmware/usbcomp_msd_cdc/inc/cdcuser.h @@ -1,63 +1,63 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: cdcuser.h - * Purpose: USB Communication Device Class User module Definitions - * Version: V1.10 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __CDCUSER_H__ -#define __CDCUSER_H__ - -/* CDC buffer handling */ -extern int CDC_RdOutBuf (char *buffer, const int *length); -extern int CDC_WrOutBuf (const char *buffer, int *length); -extern int CDC_OutBufAvailChar (int *availChar); - - -/* CDC Data In/Out Endpoint Address */ -#define CDC_DEP_IN 0x83 -#define CDC_DEP_OUT 0x03 - -/* CDC Communication In Endpoint Address */ -#define CDC_CEP_IN 0x81 - -/* CDC Requests Callback Functions */ -extern uint32_t CDC_SendEncapsulatedCommand (void); -extern uint32_t CDC_GetEncapsulatedResponse (void); -extern uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector); -extern uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector); -extern uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector); -extern uint32_t CDC_GetLineCoding (void); -extern uint32_t CDC_SetLineCoding (void); -extern uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap); -extern uint32_t CDC_SendBreak (unsigned short wDurationOfBreak); - -/* CDC Bulk Callback Functions */ -extern void CDC_BulkIn (void); -extern void CDC_BulkOut (void); - -/* CDC Notification Callback Function */ -extern void CDC_NotificationIn (void); - -/* CDC Initializtion Function */ -extern void CDC_Init (void); - -/* CDC prepare the SERAIAL_STATE */ -extern unsigned short CDC_GetSerialState (void); - -/* flow control */ -extern unsigned short CDC_DepInEmpty; // DataEndPoint IN empty - -#endif /* __CDCUSER_H__ */ - +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: cdcuser.h + * Purpose: USB Communication Device Class User module Definitions + * Version: V1.10 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __CDCUSER_H__ +#define __CDCUSER_H__ + +/* CDC buffer handling */ +extern int CDC_RdOutBuf (char *buffer, const int *length); +extern int CDC_WrOutBuf (const char *buffer, int *length); +extern int CDC_OutBufAvailChar (int *availChar); + + +/* CDC Data In/Out Endpoint Address */ +#define CDC_DEP_IN 0x83 +#define CDC_DEP_OUT 0x03 + +/* CDC Communication In Endpoint Address */ +#define CDC_CEP_IN 0x81 + +/* CDC Requests Callback Functions */ +extern uint32_t CDC_SendEncapsulatedCommand (void); +extern uint32_t CDC_GetEncapsulatedResponse (void); +extern uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector); +extern uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector); +extern uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector); +extern uint32_t CDC_GetLineCoding (void); +extern uint32_t CDC_SetLineCoding (void); +extern uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap); +extern uint32_t CDC_SendBreak (unsigned short wDurationOfBreak); + +/* CDC Bulk Callback Functions */ +extern void CDC_BulkIn (void); +extern void CDC_BulkOut (void); + +/* CDC Notification Callback Function */ +extern void CDC_NotificationIn (void); + +/* CDC Initializtion Function */ +extern void CDC_Init (void); + +/* CDC prepare the SERAIAL_STATE */ +extern unsigned short CDC_GetSerialState (void); + +/* flow control */ +extern unsigned short CDC_DepInEmpty; // DataEndPoint IN empty + +#endif /* __CDCUSER_H__ */ + diff --git a/firmware/usbcomp_msd_cdc/inc/clkconfig.h b/firmware/usbcomp_msd_cdc/inc/clkconfig.h index b4ac565..b1e2866 100644 --- a/firmware/usbcomp_msd_cdc/inc/clkconfig.h +++ b/firmware/usbcomp_msd_cdc/inc/clkconfig.h @@ -1,28 +1,28 @@ -/***************************************************************************** - * clkconfig.h: Header file for NXP LPC13xx Family Microprocessors - * - * Copyright(C) 2009, NXP Semiconductor - * All rights reserved. - * - * History - * 2009.08.20 ver 1.00 Preliminary version, first Release - * -******************************************************************************/ -#ifndef __CLKCONFIG_H -#define __CLKCONFIG_H - -#define WDTCLK_SRC_IRC_OSC 0 -#define WDTCLK_SRC_MAIN_CLK 1 -#define WDTCLK_SRC_WDT_OSC 2 - -#define CLKOUTCLK_SRC_IRC_OSC 0 -#define CLKOUTCLK_SRC_SYS_OSC 1 -#define CLKOUTCLK_SRC_WDT_OSC 2 -#define CLKOUTCLK_SRC_MAIN_CLK 3 - -void WDT_CLK_Setup(uint32_t timer_num); -void CLKOUT_Setup(uint32_t timer_num); -#endif /* end __CLKCONFIG_H */ -/***************************************************************************** -** End Of File -******************************************************************************/ +/***************************************************************************** + * clkconfig.h: Header file for NXP LPC13xx Family Microprocessors + * + * Copyright(C) 2009, NXP Semiconductor + * All rights reserved. + * + * History + * 2009.08.20 ver 1.00 Preliminary version, first Release + * +******************************************************************************/ +#ifndef __CLKCONFIG_H +#define __CLKCONFIG_H + +#define WDTCLK_SRC_IRC_OSC 0 +#define WDTCLK_SRC_MAIN_CLK 1 +#define WDTCLK_SRC_WDT_OSC 2 + +#define CLKOUTCLK_SRC_IRC_OSC 0 +#define CLKOUTCLK_SRC_SYS_OSC 1 +#define CLKOUTCLK_SRC_WDT_OSC 2 +#define CLKOUTCLK_SRC_MAIN_CLK 3 + +void WDT_CLK_Setup(uint32_t timer_num); +void CLKOUT_Setup(uint32_t timer_num); +#endif /* end __CLKCONFIG_H */ +/***************************************************************************** +** End Of File +******************************************************************************/ diff --git a/firmware/usbcomp_msd_cdc/inc/config.h b/firmware/usbcomp_msd_cdc/inc/config.h index 57ab7d0..28af6b5 100644 --- a/firmware/usbcomp_msd_cdc/inc/config.h +++ b/firmware/usbcomp_msd_cdc/inc/config.h @@ -1,41 +1,41 @@ -/***************************************************************************** - * config.h: config file for usbcdc example for NXP LPC13xx Family - * Microprocessors - * - * Copyright(C) 2008, NXP Semiconductor - * All rights reserved. - * - * History - * 2008.07.19 ver 1.00 Preliminary version, first Release - * -******************************************************************************/ - -/* -Overview: - This example shows how to use the USB driver to implement a CDC class USB peripheral. - To run this example, you must attach a USB cable to the board. See - the "Getting Started Guide" appendix for details. - -How to use: - Click the debug toolbar button. - Click the go button. - Plug the LPCXpresso's target side into a PC using a USB cable retrofit - or a 3rd party base board. - - * You should be able to see a new COM port on your PC. -*/ - -#define NXP_VID 0x1FC9 -#define MY_VID 0x???? - -#define USB_VENDOR_ID NXP_VID // Vendor ID -#define USB_PROD_ID 0x0003 // Product ID -#define USB_DEVICE 0x0100 // Device ID - -#define LED_PORT 0 // Port for led -#define LED_BIT 7 // Bit on port for led - - -/********************************************************************************* -** End Of File -*********************************************************************************/ +/***************************************************************************** + * config.h: config file for usbcdc example for NXP LPC13xx Family + * Microprocessors + * + * Copyright(C) 2008, NXP Semiconductor + * All rights reserved. + * + * History + * 2008.07.19 ver 1.00 Preliminary version, first Release + * +******************************************************************************/ + +/* +Overview: + This example shows how to use the USB driver to implement a CDC class USB peripheral. + To run this example, you must attach a USB cable to the board. See + the "Getting Started Guide" appendix for details. + +How to use: + Click the debug toolbar button. + Click the go button. + Plug the LPCXpresso's target side into a PC using a USB cable retrofit + or a 3rd party base board. + + * You should be able to see a new COM port on your PC. +*/ + +#define NXP_VID 0x1FC9 +#define MY_VID 0x???? + +#define USB_VENDOR_ID NXP_VID // Vendor ID +#define USB_PROD_ID 0x0003 // Product ID +#define USB_DEVICE 0x0100 // Device ID + +#define LED_PORT 0 // Port for led +#define LED_BIT 7 // Bit on port for led + + +/********************************************************************************* +** End Of File +*********************************************************************************/ diff --git a/firmware/usbcomp_msd_cdc/inc/memory.h b/firmware/usbcomp_msd_cdc/inc/memory.h index f5949d9..8469d90 100644 --- a/firmware/usbcomp_msd_cdc/inc/memory.h +++ b/firmware/usbcomp_msd_cdc/inc/memory.h @@ -1,20 +1,20 @@ -/*---------------------------------------------------------------------------- - * Name: memory.h - * Purpose: USB Memory Storage Demo Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -/* MSC Disk Image Definitions */ -#define MSC_ImageSize 6144 - -extern const unsigned char DiskImage[MSC_ImageSize]; /* Disk Image */ +/*---------------------------------------------------------------------------- + * Name: memory.h + * Purpose: USB Memory Storage Demo Definitions + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +/* MSC Disk Image Definitions */ +#define MSC_ImageSize 6144 + +extern const unsigned char DiskImage[MSC_ImageSize]; /* Disk Image */ diff --git a/firmware/usbcomp_msd_cdc/inc/msc.h b/firmware/usbcomp_msd_cdc/inc/msc.h index 1c674ae..4974cdd 100644 --- a/firmware/usbcomp_msd_cdc/inc/msc.h +++ b/firmware/usbcomp_msd_cdc/inc/msc.h @@ -1,101 +1,101 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: msc.h - * Purpose: USB Mass Storage Class Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __MSC_H__ -#define __MSC_H__ - - -/* MSC Subclass Codes */ -#define MSC_SUBCLASS_RBC 0x01 -#define MSC_SUBCLASS_SFF8020I_MMC2 0x02 -#define MSC_SUBCLASS_QIC157 0x03 -#define MSC_SUBCLASS_UFI 0x04 -#define MSC_SUBCLASS_SFF8070I 0x05 -#define MSC_SUBCLASS_SCSI 0x06 - -/* MSC Protocol Codes */ -#define MSC_PROTOCOL_CBI_INT 0x00 -#define MSC_PROTOCOL_CBI_NOINT 0x01 -#define MSC_PROTOCOL_BULK_ONLY 0x50 - - -/* MSC Request Codes */ -#define MSC_REQUEST_RESET 0xFF -#define MSC_REQUEST_GET_MAX_LUN 0xFE - - -/* MSC Bulk-only Stage */ -#define MSC_BS_CBW 0 /* Command Block Wrapper */ -#define MSC_BS_DATA_OUT 1 /* Data Out Phase */ -#define MSC_BS_DATA_IN 2 /* Data In Phase */ -#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */ -#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */ -#define MSC_BS_CSW 5 /* Command Status Wrapper */ -#define MSC_BS_ERROR 6 /* Error */ - - -/* Bulk-only Command Block Wrapper */ -typedef struct _MSC_CBW { - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataLength; - uint8_t bmFlags; - uint8_t bLUN; - uint8_t bCBLength; - uint8_t CB[16]; -} __attribute__((packed)) MSC_CBW; - -/* Bulk-only Command Status Wrapper */ -typedef struct _MSC_CSW { - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataResidue; - uint8_t bStatus; -} __attribute__((packed)) MSC_CSW; - -#define MSC_CBW_Signature 0x43425355 -#define MSC_CSW_Signature 0x53425355 - - -/* CSW Status Definitions */ -#define CSW_CMD_PASSED 0x00 -#define CSW_CMD_FAILED 0x01 -#define CSW_PHASE_ERROR 0x02 - - -/* SCSI Commands */ -#define SCSI_TEST_UNIT_READY 0x00 -#define SCSI_REQUEST_SENSE 0x03 -#define SCSI_FORMAT_UNIT 0x04 -#define SCSI_INQUIRY 0x12 -#define SCSI_MODE_SELECT6 0x15 -#define SCSI_MODE_SENSE6 0x1A -#define SCSI_START_STOP_UNIT 0x1B -#define SCSI_MEDIA_REMOVAL 0x1E -#define SCSI_READ_FORMAT_CAPACITIES 0x23 -#define SCSI_READ_CAPACITY 0x25 -#define SCSI_READ10 0x28 -#define SCSI_WRITE10 0x2A -#define SCSI_VERIFY10 0x2F -#define SCSI_READ12 0xA8 -#define SCSI_WRITE12 0xAA -#define SCSI_MODE_SELECT10 0x55 -#define SCSI_MODE_SENSE10 0x5A - - -#endif /* __MSC_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: msc.h + * Purpose: USB Mass Storage Class Definitions + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __MSC_H__ +#define __MSC_H__ + + +/* MSC Subclass Codes */ +#define MSC_SUBCLASS_RBC 0x01 +#define MSC_SUBCLASS_SFF8020I_MMC2 0x02 +#define MSC_SUBCLASS_QIC157 0x03 +#define MSC_SUBCLASS_UFI 0x04 +#define MSC_SUBCLASS_SFF8070I 0x05 +#define MSC_SUBCLASS_SCSI 0x06 + +/* MSC Protocol Codes */ +#define MSC_PROTOCOL_CBI_INT 0x00 +#define MSC_PROTOCOL_CBI_NOINT 0x01 +#define MSC_PROTOCOL_BULK_ONLY 0x50 + + +/* MSC Request Codes */ +#define MSC_REQUEST_RESET 0xFF +#define MSC_REQUEST_GET_MAX_LUN 0xFE + + +/* MSC Bulk-only Stage */ +#define MSC_BS_CBW 0 /* Command Block Wrapper */ +#define MSC_BS_DATA_OUT 1 /* Data Out Phase */ +#define MSC_BS_DATA_IN 2 /* Data In Phase */ +#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */ +#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */ +#define MSC_BS_CSW 5 /* Command Status Wrapper */ +#define MSC_BS_ERROR 6 /* Error */ + + +/* Bulk-only Command Block Wrapper */ +typedef struct _MSC_CBW { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} __attribute__((packed)) MSC_CBW; + +/* Bulk-only Command Status Wrapper */ +typedef struct _MSC_CSW { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} __attribute__((packed)) MSC_CSW; + +#define MSC_CBW_Signature 0x43425355 +#define MSC_CSW_Signature 0x53425355 + + +/* CSW Status Definitions */ +#define CSW_CMD_PASSED 0x00 +#define CSW_CMD_FAILED 0x01 +#define CSW_PHASE_ERROR 0x02 + + +/* SCSI Commands */ +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_FORMAT_UNIT 0x04 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SELECT6 0x15 +#define SCSI_MODE_SENSE6 0x1A +#define SCSI_START_STOP_UNIT 0x1B +#define SCSI_MEDIA_REMOVAL 0x1E +#define SCSI_READ_FORMAT_CAPACITIES 0x23 +#define SCSI_READ_CAPACITY 0x25 +#define SCSI_READ10 0x28 +#define SCSI_WRITE10 0x2A +#define SCSI_VERIFY10 0x2F +#define SCSI_READ12 0xA8 +#define SCSI_WRITE12 0xAA +#define SCSI_MODE_SELECT10 0x55 +#define SCSI_MODE_SENSE10 0x5A + + +#endif /* __MSC_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/mscuser.h b/firmware/usbcomp_msd_cdc/inc/mscuser.h index 39dbd69..1d9a1fa 100644 --- a/firmware/usbcomp_msd_cdc/inc/mscuser.h +++ b/firmware/usbcomp_msd_cdc/inc/mscuser.h @@ -1,47 +1,47 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: mscuser.h - * Purpose: Mass Storage Class Custom User Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __MSCUSER_H__ -#define __MSCUSER_H__ - - -/* Mass Storage Memory Layout */ -#define MSC_MemorySize 6144 -#define MSC_BlockSize 512 -#define MSC_BlockCount (MSC_MemorySize / MSC_BlockSize) - - -/* Max In/Out Packet Size */ -#define MSC_MAX_PACKET 64 - -/* MSC In/Out Endpoint Address */ -#define MSC_EP_IN 0x82 -#define MSC_EP_OUT 0x02 - -/* MSC Requests Callback Functions */ -extern uint32_t MSC_Reset (void); -extern uint32_t MSC_GetMaxLUN (void); - -/* MSC Bulk Callback Functions */ -extern void MSC_GetCBW (void); -extern void MSC_SetCSW (void); -extern void MSC_BulkIn (void); -extern void MSC_BulkOut(void); - - -#endif /* __MSCUSER_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: mscuser.h + * Purpose: Mass Storage Class Custom User Definitions + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __MSCUSER_H__ +#define __MSCUSER_H__ + + +/* Mass Storage Memory Layout */ +#define MSC_MemorySize 6144 +#define MSC_BlockSize 512 +#define MSC_BlockCount (MSC_MemorySize / MSC_BlockSize) + + +/* Max In/Out Packet Size */ +#define MSC_MAX_PACKET 64 + +/* MSC In/Out Endpoint Address */ +#define MSC_EP_IN 0x82 +#define MSC_EP_OUT 0x02 + +/* MSC Requests Callback Functions */ +extern uint32_t MSC_Reset (void); +extern uint32_t MSC_GetMaxLUN (void); + +/* MSC Bulk Callback Functions */ +extern void MSC_GetCBW (void); +extern void MSC_SetCSW (void); +extern void MSC_BulkIn (void); +extern void MSC_BulkOut(void); + + +#endif /* __MSCUSER_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/serial.h b/firmware/usbcomp_msd_cdc/inc/serial.h index 5817520..f8a6799 100644 --- a/firmware/usbcomp_msd_cdc/inc/serial.h +++ b/firmware/usbcomp_msd_cdc/inc/serial.h @@ -1,28 +1,28 @@ -/*---------------------------------------------------------------------------- - * Name: serial.h - * Purpose: serial port handling - * Version: V1.10 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - - -/*---------------------------------------------------------------------------- - Serial interface related prototypes - *---------------------------------------------------------------------------*/ -extern void ser_OpenPort (void); -extern void ser_ClosePort (void); -extern void ser_InitPort (unsigned long baudrate, unsigned int databits, unsigned int parity, unsigned int stopbits); -extern void ser_AvailChar (int *availChar); -extern int ser_Write (const char *buffer, int *length); -extern int ser_Read (char *buffer, const int *length); -extern void ser_LineState (unsigned short *lineState); - +/*---------------------------------------------------------------------------- + * Name: serial.h + * Purpose: serial port handling + * Version: V1.10 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + Serial interface related prototypes + *---------------------------------------------------------------------------*/ +extern void ser_OpenPort (void); +extern void ser_ClosePort (void); +extern void ser_InitPort (unsigned long baudrate, unsigned int databits, unsigned int parity, unsigned int stopbits); +extern void ser_AvailChar (int *availChar); +extern int ser_Write (const char *buffer, int *length); +extern int ser_Read (char *buffer, const int *length); +extern void ser_LineState (unsigned short *lineState); + diff --git a/firmware/usbcomp_msd_cdc/inc/type.h b/firmware/usbcomp_msd_cdc/inc/type.h index 8471782..a46427d 100644 --- a/firmware/usbcomp_msd_cdc/inc/type.h +++ b/firmware/usbcomp_msd_cdc/inc/type.h @@ -1,46 +1,46 @@ -/***************************************************************************** - * type.h: Type definition Header file for NXP Family - * Microprocessors - * - * Copyright(C) 2006, NXP Semiconductor - * All rights reserved. - * - * History - * 2009.04.01 ver 1.00 Preliminary version, first Release - * -******************************************************************************/ -#ifndef __TYPE_H__ -#define __TYPE_H__ - -// CodeRed - ifdef for GNU added to avoid potential clash with stdint.h -#if defined ( __GNUC__ ) -#include -#else - -/* exact-width signed integer types */ -typedef signed char int8_t; -typedef signed short int int16_t; -typedef signed int int32_t; -typedef signed __int64 int64_t; - - /* exact-width unsigned integer types */ -typedef unsigned char uint8_t; -typedef unsigned short int uint16_t; -typedef unsigned int uint32_t; -typedef unsigned __int64 uint64_t; - -#endif // __GNUC__ - -#ifndef NULL -#define NULL ((void *)0) -#endif - -#ifndef FALSE -#define FALSE (0) -#endif - -#ifndef TRUE -#define TRUE (1) -#endif - -#endif /* __TYPE_H__ */ +/***************************************************************************** + * type.h: Type definition Header file for NXP Family + * Microprocessors + * + * Copyright(C) 2006, NXP Semiconductor + * All rights reserved. + * + * History + * 2009.04.01 ver 1.00 Preliminary version, first Release + * +******************************************************************************/ +#ifndef __TYPE_H__ +#define __TYPE_H__ + +// CodeRed - ifdef for GNU added to avoid potential clash with stdint.h +#if defined ( __GNUC__ ) +#include +#else + +/* exact-width signed integer types */ +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef signed __int64 int64_t; + + /* exact-width unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned __int64 uint64_t; + +#endif // __GNUC__ + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (1) +#endif + +#endif /* __TYPE_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/usb.h b/firmware/usbcomp_msd_cdc/inc/usb.h index 0d7a02f..f7bea18 100644 --- a/firmware/usbcomp_msd_cdc/inc/usb.h +++ b/firmware/usbcomp_msd_cdc/inc/usb.h @@ -1,240 +1,240 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usb.h - * Purpose: USB Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __USB_H__ -#define __USB_H__ - - -typedef union { - uint16_t W; - struct { - uint8_t L; - uint8_t H; - } __attribute__((packed)) WB; -} __attribute__((packed)) WORD_BYTE; - - -/* bmRequestType.Dir */ -#define REQUEST_HOST_TO_DEVICE 0 -#define REQUEST_DEVICE_TO_HOST 1 - -/* bmRequestType.Type */ -#define REQUEST_STANDARD 0 -#define REQUEST_CLASS 1 -#define REQUEST_VENDOR 2 -#define REQUEST_RESERVED 3 - -/* bmRequestType.Recipient */ -#define REQUEST_TO_DEVICE 0 -#define REQUEST_TO_INTERFACE 1 -#define REQUEST_TO_ENDPOINT 2 -#define REQUEST_TO_OTHER 3 - -/* bmRequestType Definition */ -typedef union _REQUEST_TYPE { - struct _BM { - uint8_t Recipient : 5; - uint8_t Type : 2; - uint8_t Dir : 1; - } __attribute__((packed)) BM; - uint8_t B; -} __attribute__((packed)) REQUEST_TYPE; - -/* USB Standard Request Codes */ -#define USB_REQUEST_GET_STATUS 0 -#define USB_REQUEST_CLEAR_FEATURE 1 -#define USB_REQUEST_SET_FEATURE 3 -#define USB_REQUEST_SET_ADDRESS 5 -#define USB_REQUEST_GET_DESCRIPTOR 6 -#define USB_REQUEST_SET_DESCRIPTOR 7 -#define USB_REQUEST_GET_CONFIGURATION 8 -#define USB_REQUEST_SET_CONFIGURATION 9 -#define USB_REQUEST_GET_INTERFACE 10 -#define USB_REQUEST_SET_INTERFACE 11 -#define USB_REQUEST_SYNC_FRAME 12 - -/* USB GET_STATUS Bit Values */ -#define USB_GETSTATUS_SELF_POWERED 0x01 -#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 -#define USB_GETSTATUS_ENDPOINT_STALL 0x01 - -/* USB Standard Feature selectors */ -#define USB_FEATURE_ENDPOINT_STALL 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 - -/* USB Default Control Pipe Setup Packet */ -typedef struct _USB_SETUP_PACKET { - REQUEST_TYPE bmRequestType; - uint8_t bRequest; - WORD_BYTE wValue; - WORD_BYTE wIndex; - uint16_t wLength; -} __attribute__((packed)) USB_SETUP_PACKET; - - -/* USB Descriptor Types */ -#define USB_DEVICE_DESCRIPTOR_TYPE 1 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2 -#define USB_STRING_DESCRIPTOR_TYPE 3 -#define USB_INTERFACE_DESCRIPTOR_TYPE 4 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 5 -#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6 -#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7 -#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8 -#define USB_OTG_DESCRIPTOR_TYPE 9 -#define USB_DEBUG_DESCRIPTOR_TYPE 10 -#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11 - -/* USB Device Classes */ -#define USB_DEVICE_CLASS_RESERVED 0x00 -#define USB_DEVICE_CLASS_AUDIO 0x01 -#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 -#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 -#define USB_DEVICE_CLASS_MONITOR 0x04 -#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05 -#define USB_DEVICE_CLASS_POWER 0x06 -#define USB_DEVICE_CLASS_PRINTER 0x07 -#define USB_DEVICE_CLASS_STORAGE 0x08 -#define USB_DEVICE_CLASS_HUB 0x09 -#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF -#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF - -/* bmAttributes in Configuration Descriptor */ -#define USB_CONFIG_POWERED_MASK 0x40 -#define USB_CONFIG_BUS_POWERED 0x80 -#define USB_CONFIG_SELF_POWERED 0xC0 -#define USB_CONFIG_REMOTE_WAKEUP 0x20 - -/* bMaxPower in Configuration Descriptor */ -#define USB_CONFIG_POWER_MA(mA) ((mA)/2) - -/* bEndpointAddress in Endpoint Descriptor */ -#define USB_ENDPOINT_DIRECTION_MASK 0x80 -#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) -#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) - -/* bmAttributes in Endpoint Descriptor */ -#define USB_ENDPOINT_TYPE_MASK 0x03 -#define USB_ENDPOINT_TYPE_CONTROL 0x00 -#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 -#define USB_ENDPOINT_TYPE_BULK 0x02 -#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 -#define USB_ENDPOINT_SYNC_MASK 0x0C -#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00 -#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04 -#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08 -#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C -#define USB_ENDPOINT_USAGE_MASK 0x30 -#define USB_ENDPOINT_USAGE_DATA 0x00 -#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 -#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20 -#define USB_ENDPOINT_USAGE_RESERVED 0x30 - -/* USB Standard Device Descriptor */ -typedef struct _USB_DEVICE_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint16_t idVendor; - uint16_t idProduct; - uint16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} __attribute__((packed)) USB_DEVICE_DESCRIPTOR; - -/* USB 2.0 Device Qualifier Descriptor */ -typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; -} __attribute__((packed)) USB_DEVICE_QUALIFIER_DESCRIPTOR; - -/* USB Standard Configuration Descriptor */ -typedef struct _USB_CONFIGURATION_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; -} __attribute__((packed)) USB_CONFIGURATION_DESCRIPTOR; - -/* USB Standard Interface Association Descriptor */ -typedef struct _USB_INTERFACE_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} __attribute__((packed)) USB_INTERFACE_DESCRIPTOR; - -/* USB Interface Descriptor */ -typedef struct _USB_INTERFACE_ASSOCIATION_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bFirstInterface; - uint8_t bInterfaceCount; - uint8_t bFunctionClass; - uint8_t bFunctionSubClass; - uint8_t bFunctionProtocol; - uint8_t iFunction; -} __attribute__((packed)) USB_INTERFACE_ASSOCIATION_DESCRIPTOR; - -/* USB Standard Endpoint Descriptor */ -typedef struct _USB_ENDPOINT_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; -} __attribute__((packed)) USB_ENDPOINT_DESCRIPTOR; - -/* USB String Descriptor */ -typedef struct _USB_STRING_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bString/*[]*/; -} __attribute__((packed)) USB_STRING_DESCRIPTOR; - -/* USB Common Descriptor */ -typedef struct _USB_COMMON_DESCRIPTOR { - uint8_t bLength; - uint8_t bDescriptorType; -} __attribute__((packed)) USB_COMMON_DESCRIPTOR; - - -#endif /* __USB_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usb.h + * Purpose: USB Definitions + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __USB_H__ +#define __USB_H__ + + +typedef union { + uint16_t W; + struct { + uint8_t L; + uint8_t H; + } __attribute__((packed)) WB; +} __attribute__((packed)) WORD_BYTE; + + +/* bmRequestType.Dir */ +#define REQUEST_HOST_TO_DEVICE 0 +#define REQUEST_DEVICE_TO_HOST 1 + +/* bmRequestType.Type */ +#define REQUEST_STANDARD 0 +#define REQUEST_CLASS 1 +#define REQUEST_VENDOR 2 +#define REQUEST_RESERVED 3 + +/* bmRequestType.Recipient */ +#define REQUEST_TO_DEVICE 0 +#define REQUEST_TO_INTERFACE 1 +#define REQUEST_TO_ENDPOINT 2 +#define REQUEST_TO_OTHER 3 + +/* bmRequestType Definition */ +typedef union _REQUEST_TYPE { + struct _BM { + uint8_t Recipient : 5; + uint8_t Type : 2; + uint8_t Dir : 1; + } __attribute__((packed)) BM; + uint8_t B; +} __attribute__((packed)) REQUEST_TYPE; + +/* USB Standard Request Codes */ +#define USB_REQUEST_GET_STATUS 0 +#define USB_REQUEST_CLEAR_FEATURE 1 +#define USB_REQUEST_SET_FEATURE 3 +#define USB_REQUEST_SET_ADDRESS 5 +#define USB_REQUEST_GET_DESCRIPTOR 6 +#define USB_REQUEST_SET_DESCRIPTOR 7 +#define USB_REQUEST_GET_CONFIGURATION 8 +#define USB_REQUEST_SET_CONFIGURATION 9 +#define USB_REQUEST_GET_INTERFACE 10 +#define USB_REQUEST_SET_INTERFACE 11 +#define USB_REQUEST_SYNC_FRAME 12 + +/* USB GET_STATUS Bit Values */ +#define USB_GETSTATUS_SELF_POWERED 0x01 +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 +#define USB_GETSTATUS_ENDPOINT_STALL 0x01 + +/* USB Standard Feature selectors */ +#define USB_FEATURE_ENDPOINT_STALL 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 + +/* USB Default Control Pipe Setup Packet */ +typedef struct _USB_SETUP_PACKET { + REQUEST_TYPE bmRequestType; + uint8_t bRequest; + WORD_BYTE wValue; + WORD_BYTE wIndex; + uint16_t wLength; +} __attribute__((packed)) USB_SETUP_PACKET; + + +/* USB Descriptor Types */ +#define USB_DEVICE_DESCRIPTOR_TYPE 1 +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2 +#define USB_STRING_DESCRIPTOR_TYPE 3 +#define USB_INTERFACE_DESCRIPTOR_TYPE 4 +#define USB_ENDPOINT_DESCRIPTOR_TYPE 5 +#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6 +#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7 +#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8 +#define USB_OTG_DESCRIPTOR_TYPE 9 +#define USB_DEBUG_DESCRIPTOR_TYPE 10 +#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11 + +/* USB Device Classes */ +#define USB_DEVICE_CLASS_RESERVED 0x00 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 +#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 +#define USB_DEVICE_CLASS_MONITOR 0x04 +#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05 +#define USB_DEVICE_CLASS_POWER 0x06 +#define USB_DEVICE_CLASS_PRINTER 0x07 +#define USB_DEVICE_CLASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_HUB 0x09 +#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF +#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF + +/* bmAttributes in Configuration Descriptor */ +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 +#define USB_CONFIG_REMOTE_WAKEUP 0x20 + +/* bMaxPower in Configuration Descriptor */ +#define USB_CONFIG_POWER_MA(mA) ((mA)/2) + +/* bEndpointAddress in Endpoint Descriptor */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +/* bmAttributes in Endpoint Descriptor */ +#define USB_ENDPOINT_TYPE_MASK 0x03 +#define USB_ENDPOINT_TYPE_CONTROL 0x00 +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define USB_ENDPOINT_TYPE_BULK 0x02 +#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 +#define USB_ENDPOINT_SYNC_MASK 0x0C +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00 +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04 +#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08 +#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C +#define USB_ENDPOINT_USAGE_MASK 0x30 +#define USB_ENDPOINT_USAGE_DATA 0x00 +#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20 +#define USB_ENDPOINT_USAGE_RESERVED 0x30 + +/* USB Standard Device Descriptor */ +typedef struct _USB_DEVICE_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} __attribute__((packed)) USB_DEVICE_DESCRIPTOR; + +/* USB 2.0 Device Qualifier Descriptor */ +typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} __attribute__((packed)) USB_DEVICE_QUALIFIER_DESCRIPTOR; + +/* USB Standard Configuration Descriptor */ +typedef struct _USB_CONFIGURATION_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} __attribute__((packed)) USB_CONFIGURATION_DESCRIPTOR; + +/* USB Standard Interface Association Descriptor */ +typedef struct _USB_INTERFACE_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} __attribute__((packed)) USB_INTERFACE_DESCRIPTOR; + +/* USB Interface Descriptor */ +typedef struct _USB_INTERFACE_ASSOCIATION_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __attribute__((packed)) USB_INTERFACE_ASSOCIATION_DESCRIPTOR; + +/* USB Standard Endpoint Descriptor */ +typedef struct _USB_ENDPOINT_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} __attribute__((packed)) USB_ENDPOINT_DESCRIPTOR; + +/* USB String Descriptor */ +typedef struct _USB_STRING_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString/*[]*/; +} __attribute__((packed)) USB_STRING_DESCRIPTOR; + +/* USB Common Descriptor */ +typedef struct _USB_COMMON_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; +} __attribute__((packed)) USB_COMMON_DESCRIPTOR; + + +#endif /* __USB_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/usbcfg.h b/firmware/usbcomp_msd_cdc/inc/usbcfg.h index 1cd0cd3..572b16a 100644 --- a/firmware/usbcomp_msd_cdc/inc/usbcfg.h +++ b/firmware/usbcomp_msd_cdc/inc/usbcfg.h @@ -1,157 +1,157 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbcfg.h - * Purpose: USB Custom Configuration - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added vendor specific support - * V1.00 Initial Version - *---------------------------------------------------------------------------*/ - -#ifndef __USBCFG_H__ -#define __USBCFG_H__ - - -//*** <<< Use Configuration Wizard in Context Menu >>> *** - - -/* -// USB Configuration -// USB Power -// Default Power Setting -// <0=> Bus-powered -// <1=> Self-powered -// Max Number of Interfaces <1-256> -// Max Number of Endpoints <1-32> -// Max Endpoint 0 Packet Size -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// DMA Transfer -// Use DMA for selected Endpoints -// Endpoint 0 Out -// Endpoint 0 In -// Endpoint 1 Out -// Endpoint 1 In -// Endpoint 2 Out -// Endpoint 2 In -// Endpoint 3 Out -// Endpoint 3 In -// Endpoint 4 Out -// Endpoint 4 In -// -// -*/ - -#define USB_POWER 0 -#define USB_IF_NUM 1 -#define USB_LOGIC_EP_NUM 5 -#define USB_EP_NUM 10 -#define USB_MAX_PACKET0 64 - -/* -// USB Event Handlers -// Device Events -// Power Event -// Reset Event -// Suspend Event -// Resume Event -// Remote Wakeup Event -// Start of Frame Event -// Error Event -// -// Endpoint Events -// Endpoint 0 Event -// Endpoint 1 Event -// Endpoint 2 Event -// Endpoint 3 Event -// Endpoint 4 Event -// Endpoint 5 Event -// Endpoint 6 Event -// Endpoint 7 Event -// Endpoint 8 Event -// Endpoint 9 Event -// Endpoint 10 Event -// Endpoint 11 Event -// Endpoint 12 Event -// Endpoint 13 Event -// Endpoint 14 Event -// Endpoint 15 Event -// -// USB Core Events -// Set Configuration Event -// Set Interface Event -// Set/Clear Feature Event -// -// -*/ - -#define USB_POWER_EVENT 0 -#define USB_RESET_EVENT 1 -#define USB_SUSPEND_EVENT 1 -#define USB_RESUME_EVENT 1 -#define USB_WAKEUP_EVENT 0 -#define USB_SOF_EVENT 0 -#define USB_ERROR_EVENT 0 -#define USB_EP_EVENT 0x000f -#define USB_CONFIGURE_EVENT 1 -#define USB_INTERFACE_EVENT 0 -#define USB_FEATURE_EVENT 0 - - -/* -// USB Class Support -// enables USB Class specific Requests -// Human Interface Device (HID) -// Interface Number <0-255> -// -// Mass Storage -// Interface Number <0-255> -// -// Audio Device -// Control Interface Number <0-255> -// Streaming Interface 1 Number <0-255> -// Streaming Interface 2 Number <0-255> -// -// Communication Device -// Control Interface Number <0-255> -// Bulk Interface Number <0-255> -// Max Communication Device Buffer Size -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// -// -*/ - -#define USB_CLASS 1 -#define USB_HID 0 -#define USB_HID_IF_NUM 0 -#define USB_MSC 1 -#define USB_MSC_IF_NUM 0 -#define USB_AUDIO 0 -#define USB_ADC_CIF_NUM 0 -#define USB_ADC_SIF1_NUM 1 -#define USB_ADC_SIF2_NUM 2 -#define USB_CDC 1 -#define USB_CDC_CIF_NUM 1 -#define USB_CDC_DIF_NUM 2 -#define USB_CDC_BUFSIZE 64 - -/* -// USB Vendor Support -// enables USB Vendor specific Requests -// -*/ -#define USB_VENDOR 0 - - -#endif /* __USBCFG_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbcfg.h + * Purpose: USB Custom Configuration + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------- + * History: + * V1.20 Added vendor specific support + * V1.00 Initial Version + *---------------------------------------------------------------------------*/ + +#ifndef __USBCFG_H__ +#define __USBCFG_H__ + + +//*** <<< Use Configuration Wizard in Context Menu >>> *** + + +/* +// USB Configuration +// USB Power +// Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// Max Number of Interfaces <1-256> +// Max Number of Endpoints <1-32> +// Max Endpoint 0 Packet Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// DMA Transfer +// Use DMA for selected Endpoints +// Endpoint 0 Out +// Endpoint 0 In +// Endpoint 1 Out +// Endpoint 1 In +// Endpoint 2 Out +// Endpoint 2 In +// Endpoint 3 Out +// Endpoint 3 In +// Endpoint 4 Out +// Endpoint 4 In +// +// +*/ + +#define USB_POWER 0 +#define USB_IF_NUM 1 +#define USB_LOGIC_EP_NUM 5 +#define USB_EP_NUM 10 +#define USB_MAX_PACKET0 64 + +/* +// USB Event Handlers +// Device Events +// Power Event +// Reset Event +// Suspend Event +// Resume Event +// Remote Wakeup Event +// Start of Frame Event +// Error Event +// +// Endpoint Events +// Endpoint 0 Event +// Endpoint 1 Event +// Endpoint 2 Event +// Endpoint 3 Event +// Endpoint 4 Event +// Endpoint 5 Event +// Endpoint 6 Event +// Endpoint 7 Event +// Endpoint 8 Event +// Endpoint 9 Event +// Endpoint 10 Event +// Endpoint 11 Event +// Endpoint 12 Event +// Endpoint 13 Event +// Endpoint 14 Event +// Endpoint 15 Event +// +// USB Core Events +// Set Configuration Event +// Set Interface Event +// Set/Clear Feature Event +// +// +*/ + +#define USB_POWER_EVENT 0 +#define USB_RESET_EVENT 1 +#define USB_SUSPEND_EVENT 1 +#define USB_RESUME_EVENT 1 +#define USB_WAKEUP_EVENT 0 +#define USB_SOF_EVENT 0 +#define USB_ERROR_EVENT 0 +#define USB_EP_EVENT 0x000f +#define USB_CONFIGURE_EVENT 1 +#define USB_INTERFACE_EVENT 0 +#define USB_FEATURE_EVENT 0 + + +/* +// USB Class Support +// enables USB Class specific Requests +// Human Interface Device (HID) +// Interface Number <0-255> +// +// Mass Storage +// Interface Number <0-255> +// +// Audio Device +// Control Interface Number <0-255> +// Streaming Interface 1 Number <0-255> +// Streaming Interface 2 Number <0-255> +// +// Communication Device +// Control Interface Number <0-255> +// Bulk Interface Number <0-255> +// Max Communication Device Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// +// +*/ + +#define USB_CLASS 1 +#define USB_HID 0 +#define USB_HID_IF_NUM 0 +#define USB_MSC 1 +#define USB_MSC_IF_NUM 0 +#define USB_AUDIO 0 +#define USB_ADC_CIF_NUM 0 +#define USB_ADC_SIF1_NUM 1 +#define USB_ADC_SIF2_NUM 2 +#define USB_CDC 1 +#define USB_CDC_CIF_NUM 1 +#define USB_CDC_DIF_NUM 2 +#define USB_CDC_BUFSIZE 64 + +/* +// USB Vendor Support +// enables USB Vendor specific Requests +// +*/ +#define USB_VENDOR 0 + + +#endif /* __USBCFG_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/usbcore.h b/firmware/usbcomp_msd_cdc/inc/usbcore.h index 0cf9e6c..13ac422 100644 --- a/firmware/usbcomp_msd_cdc/inc/usbcore.h +++ b/firmware/usbcomp_msd_cdc/inc/usbcore.h @@ -1,55 +1,55 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbcore.h - * Purpose: USB Core Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __USBCORE_H__ -#define __USBCORE_H__ - - -/* USB Endpoint Data Structure */ -typedef struct _USB_EP_DATA { - uint8_t *pData; - uint16_t Count; -} USB_EP_DATA; - -/* USB Core Global Variables */ -extern uint16_t USB_DeviceStatus; -extern uint8_t USB_DeviceAddress; -extern uint8_t USB_Configuration; -extern uint32_t USB_EndPointMask; -extern uint32_t USB_EndPointHalt; -extern uint32_t USB_EndPointStall; -extern uint8_t USB_AltSetting[USB_IF_NUM]; - -/* USB Endpoint 0 Buffer */ -extern uint8_t EP0Buf[USB_MAX_PACKET0]; - -/* USB Endpoint 0 Data Info */ -extern USB_EP_DATA EP0Data; - -/* USB Setup Packet */ -extern USB_SETUP_PACKET SetupPacket; - -/* USB Core Functions */ -extern void USB_ResetCore (void); - -/* Newer C compilers make it really difficult to add - * an integer to a pointer */ -__inline void UsbAddPtr(void **vpptr, uint32_t n); - - -#endif /* __USBCORE_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbcore.h + * Purpose: USB Core Definitions + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __USBCORE_H__ +#define __USBCORE_H__ + + +/* USB Endpoint Data Structure */ +typedef struct _USB_EP_DATA { + uint8_t *pData; + uint16_t Count; +} USB_EP_DATA; + +/* USB Core Global Variables */ +extern uint16_t USB_DeviceStatus; +extern uint8_t USB_DeviceAddress; +extern uint8_t USB_Configuration; +extern uint32_t USB_EndPointMask; +extern uint32_t USB_EndPointHalt; +extern uint32_t USB_EndPointStall; +extern uint8_t USB_AltSetting[USB_IF_NUM]; + +/* USB Endpoint 0 Buffer */ +extern uint8_t EP0Buf[USB_MAX_PACKET0]; + +/* USB Endpoint 0 Data Info */ +extern USB_EP_DATA EP0Data; + +/* USB Setup Packet */ +extern USB_SETUP_PACKET SetupPacket; + +/* USB Core Functions */ +extern void USB_ResetCore (void); + +/* Newer C compilers make it really difficult to add + * an integer to a pointer */ +__inline void UsbAddPtr(void **vpptr, uint32_t n); + + +#endif /* __USBCORE_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/usbdesc.h b/firmware/usbcomp_msd_cdc/inc/usbdesc.h index c5e1faa..5f65692 100644 --- a/firmware/usbcomp_msd_cdc/inc/usbdesc.h +++ b/firmware/usbcomp_msd_cdc/inc/usbdesc.h @@ -1,36 +1,36 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbdesc.h - * Purpose: USB Descriptors Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __USBDESC_H__ -#define __USBDESC_H__ - - -#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF) - -#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR)) -#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR)) -#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR)) -#define USB_INTERFACE_ASSOCIATION_DESC_SIZE (sizeof(USB_INTERFACE_ASSOCIATION_DESCRIPTOR)) -#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR)) - -extern const uint8_t USB_DeviceDescriptor[]; -extern const uint8_t USB_ConfigDescriptor[]; -extern const uint8_t USB_StringDescriptor[]; - - -#endif /* __USBDESC_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbdesc.h + * Purpose: USB Descriptors Definitions + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __USBDESC_H__ +#define __USBDESC_H__ + + +#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF) + +#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR)) +#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR)) +#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR)) +#define USB_INTERFACE_ASSOCIATION_DESC_SIZE (sizeof(USB_INTERFACE_ASSOCIATION_DESCRIPTOR)) +#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR)) + +extern const uint8_t USB_DeviceDescriptor[]; +extern const uint8_t USB_ConfigDescriptor[]; +extern const uint8_t USB_StringDescriptor[]; + + +#endif /* __USBDESC_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/usbhw.h b/firmware/usbcomp_msd_cdc/inc/usbhw.h index e9ecb8d..f31d7d3 100644 --- a/firmware/usbcomp_msd_cdc/inc/usbhw.h +++ b/firmware/usbcomp_msd_cdc/inc/usbhw.h @@ -1,62 +1,62 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbhw.h - * Purpose: USB Hardware Layer Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added USB_ClearEPBuf - * V1.00 Initial Version - *----------------------------------------------------------------------------*/ - -#ifndef __USBHW_H__ -#define __USBHW_H__ - - -/* USB Error Codes */ -#define USB_ERR_PID 0x0001 /* PID Error */ -#define USB_ERR_UEPKT 0x0002 /* Unexpected Packet */ -#define USB_ERR_DCRC 0x0004 /* Data CRC Error */ -#define USB_ERR_TIMOUT 0x0008 /* Bus Time-out Error */ -#define USB_ERR_EOP 0x0010 /* End of Packet Error */ -#define USB_ERR_B_OVRN 0x0020 /* Buffer Overrun */ -#define USB_ERR_BTSTF 0x0040 /* Bit Stuff Error */ -#define USB_ERR_TGL 0x0080 /* Toggle Bit Error */ - -/* USB Hardware Functions */ -extern void USBIOClkConfig (void); -extern void USB_Init (void); -extern void USB_Connect (uint32_t con); -extern void USB_Reset (void); -extern void USB_Suspend (void); -extern void USB_Resume (void); -extern void USB_WakeUp (void); -extern void USB_WakeUpCfg (uint32_t cfg); -extern void USB_SetAddress (uint32_t adr); -extern void USB_Configure (uint32_t cfg); -extern void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD); -extern void USB_DirCtrlEP (uint32_t dir); -extern void USB_EnableEP (uint32_t EPNum); -extern void USB_DisableEP (uint32_t EPNum); -extern void USB_ResetEP (uint32_t EPNum); -extern void USB_SetStallEP (uint32_t EPNum); -extern void USB_ClrStallEP (uint32_t EPNum); -extern void USB_ClearEPBuf (uint32_t EPNum); -extern uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData); -extern uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt); -extern uint32_t USB_GetFrame(void); -extern void USB_IRQHandler (void); - - -#endif /* __USBHW_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbhw.h + * Purpose: USB Hardware Layer Definitions + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------- + * History: + * V1.20 Added USB_ClearEPBuf + * V1.00 Initial Version + *----------------------------------------------------------------------------*/ + +#ifndef __USBHW_H__ +#define __USBHW_H__ + + +/* USB Error Codes */ +#define USB_ERR_PID 0x0001 /* PID Error */ +#define USB_ERR_UEPKT 0x0002 /* Unexpected Packet */ +#define USB_ERR_DCRC 0x0004 /* Data CRC Error */ +#define USB_ERR_TIMOUT 0x0008 /* Bus Time-out Error */ +#define USB_ERR_EOP 0x0010 /* End of Packet Error */ +#define USB_ERR_B_OVRN 0x0020 /* Buffer Overrun */ +#define USB_ERR_BTSTF 0x0040 /* Bit Stuff Error */ +#define USB_ERR_TGL 0x0080 /* Toggle Bit Error */ + +/* USB Hardware Functions */ +extern void USBIOClkConfig (void); +extern void USB_Init (void); +extern void USB_Connect (uint32_t con); +extern void USB_Reset (void); +extern void USB_Suspend (void); +extern void USB_Resume (void); +extern void USB_WakeUp (void); +extern void USB_WakeUpCfg (uint32_t cfg); +extern void USB_SetAddress (uint32_t adr); +extern void USB_Configure (uint32_t cfg); +extern void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD); +extern void USB_DirCtrlEP (uint32_t dir); +extern void USB_EnableEP (uint32_t EPNum); +extern void USB_DisableEP (uint32_t EPNum); +extern void USB_ResetEP (uint32_t EPNum); +extern void USB_SetStallEP (uint32_t EPNum); +extern void USB_ClrStallEP (uint32_t EPNum); +extern void USB_ClearEPBuf (uint32_t EPNum); +extern uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData); +extern uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt); +extern uint32_t USB_GetFrame(void); +extern void USB_IRQHandler (void); + + +#endif /* __USBHW_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/usbreg.h b/firmware/usbcomp_msd_cdc/inc/usbreg.h index 03240be..d059e6a 100644 --- a/firmware/usbcomp_msd_cdc/inc/usbreg.h +++ b/firmware/usbcomp_msd_cdc/inc/usbreg.h @@ -1,134 +1,134 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: USBREG.H - * Purpose: USB Hardware Layer Definitions for NXP LPC13xx - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __USBREG_H -#define __USBREG_H - -/* Device Interrupt Bit Definitions */ -#define FRAME_INT (0x1<<0) -#define EP0_INT (0x1<<1) -#define EP1_INT (0x1<<2) -#define EP2_INT (0x1<<3) -#define EP3_INT (0x1<<4) -#define EP4_INT (0x1<<5) -#define EP5_INT (0x1<<6) -#define EP6_INT (0x1<<7) -#define EP7_INT (0x1<<8) -#define DEV_STAT_INT (0x1<<9) -#define CCEMTY_INT (0x1<<10) -#define CDFULL_INT (0x1<<11) -#define RxENDPKT_INT (0x1<<12) -#define TxENDPKT_INT (0x1<<13) - -/* Rx & Tx Packet Length Definitions */ -#define PKT_LNGTH_MASK 0x000003FF -#define PKT_DV 0x00000400 -#define PKT_RDY 0x00000800 - -/* USB Control Definitions */ -#define CTRL_RD_EN 0x00000001 -#define CTRL_WR_EN 0x00000002 - -/* Command Codes */ -#define CMD_SET_ADDR 0x00D00500 -#define CMD_CFG_DEV 0x00D80500 -#define CMD_SET_MODE 0x00F30500 -#define CMD_RD_INT 0x00F40500 -#define DAT_RD_INT 0x00F40200 -#define CMD_RD_FRAME 0x00F50500 -#define DAT_RD_FRAME 0x00F50200 -#define CMD_RD_CHIP_ID 0x00FD0500 -#define DAT_RD_CHIP_ID 0x00FD0200 - -#define CMD_SET_DEV_STAT 0x00FE0500 -#define CMD_GET_DEV_STAT 0x00FE0500 -#define DAT_GET_DEV_STAT 0x00FE0200 -#define CMD_GET_ERR_CODE 0x00FF0500 -#define DAT_GET_ERR_CODE 0x00FF0200 - -#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) -#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) -#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) -#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) -#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) -#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) -#define CMD_CLR_BUF 0x00F20500 -#define CMD_VALID_BUF 0x00FA0500 - -/* Device Address Register Definitions */ -#define DEV_ADDR_MASK 0x7F -#define DEV_EN 0x80 - -/* Device Configure Register Definitions */ -#define CONF_DVICE 0x01 - -/* Device Mode Register Definitions */ -#define AP_CLK 0x01 -#define INAK_CI 0x02 -#define INAK_CO 0x04 -#define INAK_AI 0x08 -#define INAK_AO 0x10 - -/* Device Status Register Definitions */ -#define DEV_CON 0x01 -#define DEV_CON_CH 0x02 -#define DEV_SUS 0x04 -#define DEV_SUS_CH 0x08 -#define DEV_RST 0x10 - -/* Error Code Register Definitions */ -#define ERR_EC_MASK 0x0F -#define ERR_EA 0x10 - -/* Error Status Register Definitions */ -#define ERR_NOERROR 0x00 -#define ERR_PID_ENCODE 0x01 -#define ERR_UNKNOWN_PID 0x02 -#define ERR_UNEXPECT_PKT 0x03 -#define ERR_TCRC 0x04 -#define ERR_DCRC 0x05 -#define ERR_TIMEOUT 0x06 -#define ERR_BABBIE 0x07 -#define ERR_EOF_PKT 0x08 -#define ERR_TX_RX_NAK 0x09 -#define ERR_SENT_STALL 0x0A -#define ERR_BUF_OVERRUN 0x0B -#define ERR_SENT_EPT_PKT 0x0C -#define ERR_BIT_STUFF 0x0D -#define ERR_SYNC 0x0E -#define ERR_TOGGLE_BIT 0x0F - -/* Endpoint Select Register Definitions */ -#define EP_SEL_F 0x01 -#define EP_SEL_ST 0x02 -#define EP_SEL_STP 0x04 -#define EP_SEL_PO 0x08 -#define EP_SEL_EPN 0x10 -#define EP_SEL_B_1_FULL 0x20 -#define EP_SEL_B_2_FULL 0x40 - -/* Endpoint Status Register Definitions */ -#define EP_STAT_ST 0x01 -#define EP_STAT_DA 0x20 -#define EP_STAT_RF_MO 0x40 -#define EP_STAT_CND_ST 0x80 - -/* Clear Buffer Register Definitions */ -#define CLR_BUF_PO 0x01 - -#endif /* __USBREG_H */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: USBREG.H + * Purpose: USB Hardware Layer Definitions for NXP LPC13xx + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#ifndef __USBREG_H +#define __USBREG_H + +/* Device Interrupt Bit Definitions */ +#define FRAME_INT (0x1<<0) +#define EP0_INT (0x1<<1) +#define EP1_INT (0x1<<2) +#define EP2_INT (0x1<<3) +#define EP3_INT (0x1<<4) +#define EP4_INT (0x1<<5) +#define EP5_INT (0x1<<6) +#define EP6_INT (0x1<<7) +#define EP7_INT (0x1<<8) +#define DEV_STAT_INT (0x1<<9) +#define CCEMTY_INT (0x1<<10) +#define CDFULL_INT (0x1<<11) +#define RxENDPKT_INT (0x1<<12) +#define TxENDPKT_INT (0x1<<13) + +/* Rx & Tx Packet Length Definitions */ +#define PKT_LNGTH_MASK 0x000003FF +#define PKT_DV 0x00000400 +#define PKT_RDY 0x00000800 + +/* USB Control Definitions */ +#define CTRL_RD_EN 0x00000001 +#define CTRL_WR_EN 0x00000002 + +/* Command Codes */ +#define CMD_SET_ADDR 0x00D00500 +#define CMD_CFG_DEV 0x00D80500 +#define CMD_SET_MODE 0x00F30500 +#define CMD_RD_INT 0x00F40500 +#define DAT_RD_INT 0x00F40200 +#define CMD_RD_FRAME 0x00F50500 +#define DAT_RD_FRAME 0x00F50200 +#define CMD_RD_CHIP_ID 0x00FD0500 +#define DAT_RD_CHIP_ID 0x00FD0200 + +#define CMD_SET_DEV_STAT 0x00FE0500 +#define CMD_GET_DEV_STAT 0x00FE0500 +#define DAT_GET_DEV_STAT 0x00FE0200 +#define CMD_GET_ERR_CODE 0x00FF0500 +#define DAT_GET_ERR_CODE 0x00FF0200 + +#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) +#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) +#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) +#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) +#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) +#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) +#define CMD_CLR_BUF 0x00F20500 +#define CMD_VALID_BUF 0x00FA0500 + +/* Device Address Register Definitions */ +#define DEV_ADDR_MASK 0x7F +#define DEV_EN 0x80 + +/* Device Configure Register Definitions */ +#define CONF_DVICE 0x01 + +/* Device Mode Register Definitions */ +#define AP_CLK 0x01 +#define INAK_CI 0x02 +#define INAK_CO 0x04 +#define INAK_AI 0x08 +#define INAK_AO 0x10 + +/* Device Status Register Definitions */ +#define DEV_CON 0x01 +#define DEV_CON_CH 0x02 +#define DEV_SUS 0x04 +#define DEV_SUS_CH 0x08 +#define DEV_RST 0x10 + +/* Error Code Register Definitions */ +#define ERR_EC_MASK 0x0F +#define ERR_EA 0x10 + +/* Error Status Register Definitions */ +#define ERR_NOERROR 0x00 +#define ERR_PID_ENCODE 0x01 +#define ERR_UNKNOWN_PID 0x02 +#define ERR_UNEXPECT_PKT 0x03 +#define ERR_TCRC 0x04 +#define ERR_DCRC 0x05 +#define ERR_TIMEOUT 0x06 +#define ERR_BABBIE 0x07 +#define ERR_EOF_PKT 0x08 +#define ERR_TX_RX_NAK 0x09 +#define ERR_SENT_STALL 0x0A +#define ERR_BUF_OVERRUN 0x0B +#define ERR_SENT_EPT_PKT 0x0C +#define ERR_BIT_STUFF 0x0D +#define ERR_SYNC 0x0E +#define ERR_TOGGLE_BIT 0x0F + +/* Endpoint Select Register Definitions */ +#define EP_SEL_F 0x01 +#define EP_SEL_ST 0x02 +#define EP_SEL_STP 0x04 +#define EP_SEL_PO 0x08 +#define EP_SEL_EPN 0x10 +#define EP_SEL_B_1_FULL 0x20 +#define EP_SEL_B_2_FULL 0x40 + +/* Endpoint Status Register Definitions */ +#define EP_STAT_ST 0x01 +#define EP_STAT_DA 0x20 +#define EP_STAT_RF_MO 0x40 +#define EP_STAT_CND_ST 0x80 + +/* Clear Buffer Register Definitions */ +#define CLR_BUF_PO 0x01 + +#endif /* __USBREG_H */ diff --git a/firmware/usbcomp_msd_cdc/inc/usbuser.h b/firmware/usbcomp_msd_cdc/inc/usbuser.h index 10b33ad..e4109ec 100644 --- a/firmware/usbcomp_msd_cdc/inc/usbuser.h +++ b/firmware/usbcomp_msd_cdc/inc/usbuser.h @@ -1,57 +1,57 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: USBUSER.H - * Purpose: USB Custom User Definitions - * Version: V1.10 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2005-2009 Keil Software. - *---------------------------------------------------------------------------*/ - -#ifndef __USBUSER_H__ -#define __USBUSER_H__ - - -/* USB Device Events Callback Functions */ -extern void USB_Power_Event (uint32_t power); -extern void USB_Reset_Event (void); -extern void USB_Suspend_Event (void); -extern void USB_Resume_Event (void); -extern void USB_WakeUp_Event (void); -extern void USB_SOF_Event (void); -extern void USB_Error_Event (uint32_t error); - -/* USB Endpoint Callback Events */ -#define USB_EVT_SETUP 1 /* Setup Packet */ -#define USB_EVT_OUT 2 /* OUT Packet */ -#define USB_EVT_IN 3 /* IN Packet */ -#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */ -#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */ -#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */ -#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */ - -/* USB Endpoint Events Callback Pointers */ -extern void (* const USB_P_EP[USB_LOGIC_EP_NUM])(uint32_t event); - -/* USB Endpoint Events Callback Functions */ -extern void USB_EndPoint0 (uint32_t event); -extern void USB_EndPoint1 (uint32_t event); -extern void USB_EndPoint2 (uint32_t event); -extern void USB_EndPoint3 (uint32_t event); -extern void USB_EndPoint4 (uint32_t event); - -/* USB Core Events Callback Functions */ -extern void USB_Configure_Event (void); -extern void USB_Interface_Event (void); -extern void USB_Feature_Event (void); - - -#endif /* __USBUSER_H__ */ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: USBUSER.H + * Purpose: USB Custom User Definitions + * Version: V1.10 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2005-2009 Keil Software. + *---------------------------------------------------------------------------*/ + +#ifndef __USBUSER_H__ +#define __USBUSER_H__ + + +/* USB Device Events Callback Functions */ +extern void USB_Power_Event (uint32_t power); +extern void USB_Reset_Event (void); +extern void USB_Suspend_Event (void); +extern void USB_Resume_Event (void); +extern void USB_WakeUp_Event (void); +extern void USB_SOF_Event (void); +extern void USB_Error_Event (uint32_t error); + +/* USB Endpoint Callback Events */ +#define USB_EVT_SETUP 1 /* Setup Packet */ +#define USB_EVT_OUT 2 /* OUT Packet */ +#define USB_EVT_IN 3 /* IN Packet */ +#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */ +#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */ +#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */ +#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */ + +/* USB Endpoint Events Callback Pointers */ +extern void (* const USB_P_EP[USB_LOGIC_EP_NUM])(uint32_t event); + +/* USB Endpoint Events Callback Functions */ +extern void USB_EndPoint0 (uint32_t event); +extern void USB_EndPoint1 (uint32_t event); +extern void USB_EndPoint2 (uint32_t event); +extern void USB_EndPoint3 (uint32_t event); +extern void USB_EndPoint4 (uint32_t event); + +/* USB Core Events Callback Functions */ +extern void USB_Configure_Event (void); +extern void USB_Interface_Event (void); +extern void USB_Feature_Event (void); + + +#endif /* __USBUSER_H__ */ diff --git a/firmware/usbcomp_msd_cdc/inc/vcomdemo.h b/firmware/usbcomp_msd_cdc/inc/vcomdemo.h index 75cbbd8..63b3b61 100644 --- a/firmware/usbcomp_msd_cdc/inc/vcomdemo.h +++ b/firmware/usbcomp_msd_cdc/inc/vcomdemo.h @@ -1,31 +1,31 @@ -/*---------------------------------------------------------------------------- - * Name: vcomdemo.h - * Purpose: USB virtual COM port Demo Definitions - * Version: V1.02 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -/* Push Button Definitions */ -#define S2 0x00000400 /* P2.10 */ - -/* LED Definitions */ -#define LED1 0x00000001 /* P2.00 */ -#define LED2 0x00000002 /* P2.01 */ -#define LED3 0x00000004 /* P2.02 */ -#define LED4 0x00000008 /* P2.03 */ -#define LED5 0x00000010 /* P2.04 */ -#define LED6 0x00000020 /* P2.05 */ -#define LED7 0x00000040 /* P2.06 */ -#define LED8 0x00000080 /* P2.07 */ - -#define LEDMSK 0x000000FF /* P2.0..7 */ - +/*---------------------------------------------------------------------------- + * Name: vcomdemo.h + * Purpose: USB virtual COM port Demo Definitions + * Version: V1.02 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +/* Push Button Definitions */ +#define S2 0x00000400 /* P2.10 */ + +/* LED Definitions */ +#define LED1 0x00000001 /* P2.00 */ +#define LED2 0x00000002 /* P2.01 */ +#define LED3 0x00000004 /* P2.02 */ +#define LED4 0x00000008 /* P2.03 */ +#define LED5 0x00000010 /* P2.04 */ +#define LED6 0x00000020 /* P2.05 */ +#define LED7 0x00000040 /* P2.06 */ +#define LED8 0x00000080 /* P2.07 */ + +#define LEDMSK 0x000000FF /* P2.0..7 */ + diff --git a/firmware/usbcomp_msd_cdc/lpc134x-vcom.inf b/firmware/usbcomp_msd_cdc/lpc134x-vcom.inf deleted file mode 100644 index 81e585d..0000000 --- a/firmware/usbcomp_msd_cdc/lpc134x-vcom.inf +++ /dev/null @@ -1,60 +0,0 @@ -[Version] -Signature="$Windows NT$" -Class=Ports -ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} -Provider=%NXP% -;LayoutFile=layout.inf -DriverVer=01/06/07 - -[Manufacturer] -%NXP%=DeviceList - -[DestinationDirs] -DefaultDestDir=12 - -[SourceDisksFiles] - -[SourceDisksNames] - -[DeviceList] -%DESCRIPTION%=LPC134xUSB, USB\VID_1FC9&PID_0003&MI_01 - -;------------------------------------------------------------------------------ -; Windows 2000/XP Sections -;------------------------------------------------------------------------------ - -[LPC134xUSB.nt] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles -AddReg=LPC134xUSB.nt.AddReg - -[DriverCopyFiles] -usbser.sys,,,0x20 - -[LPC134xUSB.nt.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[LPC134xUSB.nt.Services] -include=mdmcpq.inf -AddService=usbser, 0x00000002, DriverService - - -[LPC134xUSB.nt.HW] -include=mdmcpq.inf - -[DriverService] -DisplayName=%DESCRIPTION% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\usbser.sys - -;------------------------------------------------------------------------------ -; String Definitions -;------------------------------------------------------------------------------ - -[Strings] -NXP="NXP - Founded by Philips" -DESCRIPTION="LPC134x USB VCom Port" diff --git a/firmware/usbcomp_msd_cdc/readme.txt b/firmware/usbcomp_msd_cdc/readme.txt index 3427ad7..c07f8c9 100644 --- a/firmware/usbcomp_msd_cdc/readme.txt +++ b/firmware/usbcomp_msd_cdc/readme.txt @@ -1,39 +1,39 @@ -usbcomp_msd_cdc -===================== -This project implements a USB composite class device that includes -a mass storage device and a virtual COM device. - -To run this example, you must attach a USB cable to the board. See -the "Getting Started Guide" appendix for details. You may also -connect the LPCXpresso board to a base board from a 3rd party tool -partner. - -When downloaded to the board and executed, the PC will first recognize -a USB mass storage device and mount a new drive that contains a text -file, and then it will recognize a USB "VCOM" device and ask for a -driver. Point windows to the .inf file in the usbcomp_msd_cdc project -directory to cause Windows to install the default USB serial driver. - -At this point, you should be able to read/write files in the newly -mounted drive and send/receive characters through the USB virtual -COM port at the same time. The transmit baud rate will equal the -CDC port configured baud rate. - -One thing we have seen that can cause trouble with the USB examples -is the Windows driver install. Since the example projects all use -the same USB Vendor ID and Product ID, if you try out the HID -example and then try out the CDC example, Windows may try -to use the HID driver it had already installed with the CDC -example code. To fix this, go to the Windows Device Manager, -find the broken "HID" device and select "Uninstall." Then unplug the -device and plug it back in. Windows should correctly identify the -device as being a CDC device and install the correct -driver. - -The project makes use of code from the following library projects: -- CMSISv1p30_LPC13xx : for CMSIS 1.30 files relevant to LPC13xx - -This library project must exist in the same workspace in order -for the project to successfully build. - -For more details, read the comments in config.h +usbcomp_msd_cdc +===================== +This project implements a USB composite class device that includes +a mass storage device and a virtual COM device. + +To run this example, you must attach a USB cable to the board. See +the "Getting Started Guide" appendix for details. You may also +connect the LPCXpresso board to a base board from a 3rd party tool +partner. + +When downloaded to the board and executed, the PC will first recognize +a USB mass storage device and mount a new drive that contains a text +file, and then it will recognize a USB "VCOM" device and ask for a +driver. Point windows to the .inf file in the usbcomp_msd_cdc project +directory to cause Windows to install the default USB serial driver. + +At this point, you should be able to read/write files in the newly +mounted drive and send/receive characters through the USB virtual +COM port at the same time. The transmit baud rate will equal the +CDC port configured baud rate. + +One thing we have seen that can cause trouble with the USB examples +is the Windows driver install. Since the example projects all use +the same USB Vendor ID and Product ID, if you try out the HID +example and then try out the CDC example, Windows may try +to use the HID driver it had already installed with the CDC +example code. To fix this, go to the Windows Device Manager, +find the broken "HID" device and select "Uninstall." Then unplug the +device and plug it back in. Windows should correctly identify the +device as being a CDC device and install the correct +driver. + +The project makes use of code from the following library projects: +- CMSISv1p30_LPC13xx : for CMSIS 1.30 files relevant to LPC13xx + +This library project must exist in the same workspace in order +for the project to successfully build. + +For more details, read the comments in config.h diff --git a/firmware/usbcomp_msd_cdc/src/DiskImg.c b/firmware/usbcomp_msd_cdc/src/DiskImg.c index a62ebae..01d9819 100644 --- a/firmware/usbcomp_msd_cdc/src/DiskImg.c +++ b/firmware/usbcomp_msd_cdc/src/DiskImg.c @@ -1,166 +1,166 @@ -/* Disk Image */ - -#include "memory.h" - -const unsigned char DiskImage[MSC_ImageSize] = { -0xEB,0x3C,0x90,0x4D,0x53,0x44,0x4F,0x53,0x35,0x2E,0x30,0x00,0x02,0x01,0x01,0x00, -0x01,0x10,0x00,0x20,0x00,0xF8,0x02,0x00,0x01,0x00,0x01,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x74,0x19,0x02,0x27,0x4C,0x50,0x43,0x32,0x33, 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Version: V1.10 - *---------------------------------------------------------------------------- -* This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include "type.h" - -#include "usb.h" -#include "usbhw.h" -#include "usbcfg.h" -#include "usbcore.h" -#include "cdc.h" -#include "cdcuser.h" -#include "serial.h" - - -unsigned char BulkBufIn [USB_CDC_BUFSIZE]; // Buffer to store USB IN packet -unsigned char BulkBufOut [USB_CDC_BUFSIZE]; // Buffer to store USB OUT packet -unsigned char NotificationBuf [10]; - -CDC_LINE_CODING CDC_LineCoding = {9600, 0, 0, 8}; -unsigned short CDC_SerialState = 0x0000; -unsigned short CDC_DepInEmpty = 1; // Data IN EP is empty - -/*---------------------------------------------------------------------------- - We need a buffer for incomming data on USB port because USB receives - much faster than UART transmits - *---------------------------------------------------------------------------*/ -/* Buffer masks */ -#define CDC_BUF_SIZE (64) // Output buffer in bytes (power 2) - // large enough for file transfer -#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul) - -/* Buffer read / write macros */ -#define CDC_BUF_RESET(cdcBuf) (cdcBuf.rdIdx = cdcBuf.wrIdx = 0) -#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.wrIdx++] = (dataIn)) -#define CDC_BUF_RD(cdcBuf) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.rdIdx++]) -#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx) -#define CDC_BUF_FULL(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx+1) -#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf.wrIdx - cdcBuf.rdIdx)) - - -// CDC output buffer -typedef struct __CDC_BUF_T { - unsigned char data[CDC_BUF_SIZE]; - unsigned int wrIdx; - unsigned int rdIdx; -} CDC_BUF_T; - -CDC_BUF_T CDC_OutBuf; // buffer for all CDC Out data - -/*---------------------------------------------------------------------------- - read data from CDC_OutBuf - *---------------------------------------------------------------------------*/ -int CDC_RdOutBuf (char *buffer, const int *length) { - int bytesToRead, bytesRead; - - /* Read *length bytes, block if *bytes are not avaialable */ - bytesToRead = *length; - bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length); - bytesRead = bytesToRead; - - - // ... add code to check for underrun - - while (bytesToRead--) { - *buffer++ = CDC_BUF_RD(CDC_OutBuf); - } - return (bytesRead); -} - -/*---------------------------------------------------------------------------- - write data to CDC_OutBuf - *---------------------------------------------------------------------------*/ -int CDC_WrOutBuf (const char *buffer, int *length) { - int bytesToWrite, bytesWritten; - - // Write *length bytes - bytesToWrite = *length; - bytesWritten = bytesToWrite; - - - // ... add code to check for overwrite - - while (bytesToWrite) { - CDC_BUF_WR(CDC_OutBuf, *buffer++); // Copy Data to buffer - bytesToWrite--; - } - - return (bytesWritten); -} - -/*---------------------------------------------------------------------------- - check if character(s) are available at CDC_OutBuf - *---------------------------------------------------------------------------*/ -int CDC_OutBufAvailChar (int *availChar) { - - *availChar = CDC_BUF_COUNT(CDC_OutBuf); - - return (0); -} -/* end Buffer handling */ - - -/*---------------------------------------------------------------------------- - CDC Initialisation - Initializes the data structures and serial port - Parameters: None - Return Value: None - *---------------------------------------------------------------------------*/ -void CDC_Init (void) { - - ser_OpenPort (); - ser_InitPort (CDC_LineCoding.dwDTERate, - CDC_LineCoding.bDataBits, - CDC_LineCoding.bParityType, - CDC_LineCoding.bCharFormat); - - CDC_DepInEmpty = 1; - CDC_SerialState = CDC_GetSerialState(); - - CDC_BUF_RESET(CDC_OutBuf); -} - - -/*---------------------------------------------------------------------------- - CDC SendEncapsulatedCommand Request Callback - Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request - Parameters: None (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SendEncapsulatedCommand (void) { - - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC GetEncapsulatedResponse Request Callback - Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request - Parameters: None (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_GetEncapsulatedResponse (void) { - - /* ... add code to handle request */ - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SetCommFeature Request Callback - Called automatically on CDC Set_COMM_FATURE Request - Parameters: FeatureSelector - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector) { - - /* ... add code to handle request */ - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC GetCommFeature Request Callback - Called automatically on CDC Get_COMM_FATURE Request - Parameters: FeatureSelector - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector) { - - /* ... add code to handle request */ - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC ClearCommFeature Request Callback - Called automatically on CDC CLEAR_COMM_FATURE Request - Parameters: FeatureSelector - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector) { - - /* ... add code to handle request */ - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SetLineCoding Request Callback - Called automatically on CDC SET_LINE_CODING Request - Parameters: none (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SetLineCoding (void) { - - CDC_LineCoding.dwDTERate = (EP0Buf[0] << 0) - | (EP0Buf[1] << 8) - | (EP0Buf[2] << 16) - | (EP0Buf[3] << 24); - CDC_LineCoding.bCharFormat = EP0Buf[4]; - CDC_LineCoding.bParityType = EP0Buf[5]; - CDC_LineCoding.bDataBits = EP0Buf[6]; - - ser_ClosePort(); - ser_OpenPort (); - ser_InitPort (CDC_LineCoding.dwDTERate, - CDC_LineCoding.bDataBits, - CDC_LineCoding.bParityType, - CDC_LineCoding.bCharFormat); - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC GetLineCoding Request Callback - Called automatically on CDC GET_LINE_CODING Request - Parameters: None (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_GetLineCoding (void) { - - EP0Buf[0] = (CDC_LineCoding.dwDTERate >> 0) & 0xFF; - EP0Buf[1] = (CDC_LineCoding.dwDTERate >> 8) & 0xFF; - EP0Buf[2] = (CDC_LineCoding.dwDTERate >> 16) & 0xFF; - EP0Buf[3] = (CDC_LineCoding.dwDTERate >> 24) & 0xFF; - EP0Buf[4] = CDC_LineCoding.bCharFormat; - EP0Buf[5] = CDC_LineCoding.bParityType; - EP0Buf[6] = CDC_LineCoding.bDataBits; - - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SetControlLineState Request Callback - Called automatically on CDC SET_CONTROL_LINE_STATE Request - Parameters: ControlSignalBitmap - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap) { - - /* ... add code to handle request */ - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SendBreak Request Callback - Called automatically on CDC Set_COMM_FATURE Request - Parameters: 0xFFFF start of Break - 0x0000 stop of Break - 0x#### Duration of Break - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SendBreak (unsigned short wDurationOfBreak) { - - /* ... add code to handle request */ - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC_BulkIn call on DataIn Request - Parameters: none - Return Value: none - *---------------------------------------------------------------------------*/ -void CDC_BulkIn(void) { - int numBytesRead, numBytesAvail; - - ser_AvailChar (&numBytesAvail); - - // ... add code to check for overwrite - - numBytesRead = ser_Read ((char *)&BulkBufIn[0], &numBytesAvail); - - // send over USB - if (numBytesRead > 0) { - USB_WriteEP (CDC_DEP_IN, &BulkBufIn[0], numBytesRead); - } - else { - CDC_DepInEmpty = 1; - } -} - - -/*---------------------------------------------------------------------------- - CDC_BulkOut call on DataOut Request - Parameters: none - Return Value: none - *---------------------------------------------------------------------------*/ -void CDC_BulkOut(void) { - int numBytesRead; - - // get data from USB into intermediate buffer - numBytesRead = USB_ReadEP(CDC_DEP_OUT, &BulkBufOut[0]); - - // ... add code to check for overwrite - - // store data in a buffer to transmit it over serial interface - CDC_WrOutBuf ((char *)&BulkBufOut[0], &numBytesRead); - -} - - -/*---------------------------------------------------------------------------- - Get the SERIAL_STATE as defined in usbcdc11.pdf, 6.3.5, Table 69. - Parameters: none - Return Value: SerialState as defined in usbcdc11.pdf - *---------------------------------------------------------------------------*/ -unsigned short CDC_GetSerialState (void) { - unsigned short temp; - - CDC_SerialState = 0; - ser_LineState (&temp); - - if (temp & 0x8000) CDC_SerialState |= CDC_SERIAL_STATE_RX_CARRIER; - if (temp & 0x2000) CDC_SerialState |= CDC_SERIAL_STATE_TX_CARRIER; - if (temp & 0x0010) CDC_SerialState |= CDC_SERIAL_STATE_BREAK; - if (temp & 0x4000) CDC_SerialState |= CDC_SERIAL_STATE_RING; - if (temp & 0x0008) CDC_SerialState |= CDC_SERIAL_STATE_FRAMING; - if (temp & 0x0004) CDC_SerialState |= CDC_SERIAL_STATE_PARITY; - if (temp & 0x0002) CDC_SerialState |= CDC_SERIAL_STATE_OVERRUN; - - return (CDC_SerialState); -} - - -/*---------------------------------------------------------------------------- - Send the SERIAL_STATE notification as defined in usbcdc11.pdf, 6.3.5. - *---------------------------------------------------------------------------*/ -void CDC_NotificationIn (void) { - - NotificationBuf[0] = 0xA1; // bmRequestType - NotificationBuf[1] = CDC_NOTIFICATION_SERIAL_STATE; // bNotification (SERIAL_STATE) - NotificationBuf[2] = 0x00; // wValue - NotificationBuf[3] = 0x00; - NotificationBuf[4] = 0x00; // wIndex (Interface #, LSB first) - NotificationBuf[5] = 0x00; - NotificationBuf[6] = 0x02; // wLength (Data length = 2 bytes, LSB first) - NotificationBuf[7] = 0x00; - NotificationBuf[8] = (CDC_SerialState >> 0) & 0xFF; // UART State Bitmap (16bits, LSB first) - NotificationBuf[9] = (CDC_SerialState >> 8) & 0xFF; - - USB_WriteEP (CDC_CEP_IN, &NotificationBuf[0], 10); // send notification -} +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: cdcuser.c + * Purpose: USB Communication Device Class User module + * Version: V1.10 + *---------------------------------------------------------------------------- +* This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include "type.h" + +#include "usb.h" +#include "usbhw.h" +#include "usbcfg.h" +#include "usbcore.h" +#include "cdc.h" +#include "cdcuser.h" +#include "serial.h" + + +unsigned char BulkBufIn [USB_CDC_BUFSIZE]; // Buffer to store USB IN packet +unsigned char BulkBufOut [USB_CDC_BUFSIZE]; // Buffer to store USB OUT packet +unsigned char NotificationBuf [10]; + +CDC_LINE_CODING CDC_LineCoding = {9600, 0, 0, 8}; +unsigned short CDC_SerialState = 0x0000; +unsigned short CDC_DepInEmpty = 1; // Data IN EP is empty + +/*---------------------------------------------------------------------------- + We need a buffer for incomming data on USB port because USB receives + much faster than UART transmits + *---------------------------------------------------------------------------*/ +/* Buffer masks */ +#define CDC_BUF_SIZE (64) // Output buffer in bytes (power 2) + // large enough for file transfer +#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul) + +/* Buffer read / write macros */ +#define CDC_BUF_RESET(cdcBuf) (cdcBuf.rdIdx = cdcBuf.wrIdx = 0) +#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.wrIdx++] = (dataIn)) +#define CDC_BUF_RD(cdcBuf) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.rdIdx++]) +#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx) +#define CDC_BUF_FULL(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx+1) +#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf.wrIdx - cdcBuf.rdIdx)) + + +// CDC output buffer +typedef struct __CDC_BUF_T { + unsigned char data[CDC_BUF_SIZE]; + unsigned int wrIdx; + unsigned int rdIdx; +} CDC_BUF_T; + +CDC_BUF_T CDC_OutBuf; // buffer for all CDC Out data + +/*---------------------------------------------------------------------------- + read data from CDC_OutBuf + *---------------------------------------------------------------------------*/ +int CDC_RdOutBuf (char *buffer, const int *length) { + int bytesToRead, bytesRead; + + /* Read *length bytes, block if *bytes are not avaialable */ + bytesToRead = *length; + bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length); + bytesRead = bytesToRead; + + + // ... add code to check for underrun + + while (bytesToRead--) { + *buffer++ = CDC_BUF_RD(CDC_OutBuf); + } + return (bytesRead); +} + +/*---------------------------------------------------------------------------- + write data to CDC_OutBuf + *---------------------------------------------------------------------------*/ +int CDC_WrOutBuf (const char *buffer, int *length) { + int bytesToWrite, bytesWritten; + + // Write *length bytes + bytesToWrite = *length; + bytesWritten = bytesToWrite; + + + // ... add code to check for overwrite + + while (bytesToWrite) { + CDC_BUF_WR(CDC_OutBuf, *buffer++); // Copy Data to buffer + bytesToWrite--; + } + + return (bytesWritten); +} + +/*---------------------------------------------------------------------------- + check if character(s) are available at CDC_OutBuf + *---------------------------------------------------------------------------*/ +int CDC_OutBufAvailChar (int *availChar) { + + *availChar = CDC_BUF_COUNT(CDC_OutBuf); + + return (0); +} +/* end Buffer handling */ + + +/*---------------------------------------------------------------------------- + CDC Initialisation + Initializes the data structures and serial port + Parameters: None + Return Value: None + *---------------------------------------------------------------------------*/ +void CDC_Init (void) { + + ser_OpenPort (); + ser_InitPort (CDC_LineCoding.dwDTERate, + CDC_LineCoding.bDataBits, + CDC_LineCoding.bParityType, + CDC_LineCoding.bCharFormat); + + CDC_DepInEmpty = 1; + CDC_SerialState = CDC_GetSerialState(); + + CDC_BUF_RESET(CDC_OutBuf); +} + + +/*---------------------------------------------------------------------------- + CDC SendEncapsulatedCommand Request Callback + Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request + Parameters: None (global SetupPacket and EP0Buf) + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_SendEncapsulatedCommand (void) { + + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC GetEncapsulatedResponse Request Callback + Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request + Parameters: None (global SetupPacket and EP0Buf) + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_GetEncapsulatedResponse (void) { + + /* ... add code to handle request */ + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC SetCommFeature Request Callback + Called automatically on CDC Set_COMM_FATURE Request + Parameters: FeatureSelector + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector) { + + /* ... add code to handle request */ + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC GetCommFeature Request Callback + Called automatically on CDC Get_COMM_FATURE Request + Parameters: FeatureSelector + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector) { + + /* ... add code to handle request */ + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC ClearCommFeature Request Callback + Called automatically on CDC CLEAR_COMM_FATURE Request + Parameters: FeatureSelector + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector) { + + /* ... add code to handle request */ + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC SetLineCoding Request Callback + Called automatically on CDC SET_LINE_CODING Request + Parameters: none (global SetupPacket and EP0Buf) + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_SetLineCoding (void) { + + CDC_LineCoding.dwDTERate = (EP0Buf[0] << 0) + | (EP0Buf[1] << 8) + | (EP0Buf[2] << 16) + | (EP0Buf[3] << 24); + CDC_LineCoding.bCharFormat = EP0Buf[4]; + CDC_LineCoding.bParityType = EP0Buf[5]; + CDC_LineCoding.bDataBits = EP0Buf[6]; + + ser_ClosePort(); + ser_OpenPort (); + ser_InitPort (CDC_LineCoding.dwDTERate, + CDC_LineCoding.bDataBits, + CDC_LineCoding.bParityType, + CDC_LineCoding.bCharFormat); + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC GetLineCoding Request Callback + Called automatically on CDC GET_LINE_CODING Request + Parameters: None (global SetupPacket and EP0Buf) + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_GetLineCoding (void) { + + EP0Buf[0] = (CDC_LineCoding.dwDTERate >> 0) & 0xFF; + EP0Buf[1] = (CDC_LineCoding.dwDTERate >> 8) & 0xFF; + EP0Buf[2] = (CDC_LineCoding.dwDTERate >> 16) & 0xFF; + EP0Buf[3] = (CDC_LineCoding.dwDTERate >> 24) & 0xFF; + EP0Buf[4] = CDC_LineCoding.bCharFormat; + EP0Buf[5] = CDC_LineCoding.bParityType; + EP0Buf[6] = CDC_LineCoding.bDataBits; + + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC SetControlLineState Request Callback + Called automatically on CDC SET_CONTROL_LINE_STATE Request + Parameters: ControlSignalBitmap + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap) { + + /* ... add code to handle request */ + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC SendBreak Request Callback + Called automatically on CDC Set_COMM_FATURE Request + Parameters: 0xFFFF start of Break + 0x0000 stop of Break + 0x#### Duration of Break + Return Value: TRUE - Success, FALSE - Error + *---------------------------------------------------------------------------*/ +uint32_t CDC_SendBreak (unsigned short wDurationOfBreak) { + + /* ... add code to handle request */ + return (TRUE); +} + + +/*---------------------------------------------------------------------------- + CDC_BulkIn call on DataIn Request + Parameters: none + Return Value: none + *---------------------------------------------------------------------------*/ +void CDC_BulkIn(void) { + int numBytesRead, numBytesAvail; + + ser_AvailChar (&numBytesAvail); + + // ... add code to check for overwrite + + numBytesRead = ser_Read ((char *)&BulkBufIn[0], &numBytesAvail); + + // send over USB + if (numBytesRead > 0) { + USB_WriteEP (CDC_DEP_IN, &BulkBufIn[0], numBytesRead); + } + else { + CDC_DepInEmpty = 1; + } +} + + +/*---------------------------------------------------------------------------- + CDC_BulkOut call on DataOut Request + Parameters: none + Return Value: none + *---------------------------------------------------------------------------*/ +void CDC_BulkOut(void) { + int numBytesRead; + + // get data from USB into intermediate buffer + numBytesRead = USB_ReadEP(CDC_DEP_OUT, &BulkBufOut[0]); + + // ... add code to check for overwrite + + // store data in a buffer to transmit it over serial interface + CDC_WrOutBuf ((char *)&BulkBufOut[0], &numBytesRead); + +} + + +/*---------------------------------------------------------------------------- + Get the SERIAL_STATE as defined in usbcdc11.pdf, 6.3.5, Table 69. + Parameters: none + Return Value: SerialState as defined in usbcdc11.pdf + *---------------------------------------------------------------------------*/ +unsigned short CDC_GetSerialState (void) { + unsigned short temp; + + CDC_SerialState = 0; + ser_LineState (&temp); + + if (temp & 0x8000) CDC_SerialState |= CDC_SERIAL_STATE_RX_CARRIER; + if (temp & 0x2000) CDC_SerialState |= CDC_SERIAL_STATE_TX_CARRIER; + if (temp & 0x0010) CDC_SerialState |= CDC_SERIAL_STATE_BREAK; + if (temp & 0x4000) CDC_SerialState |= CDC_SERIAL_STATE_RING; + if (temp & 0x0008) CDC_SerialState |= CDC_SERIAL_STATE_FRAMING; + if (temp & 0x0004) CDC_SerialState |= CDC_SERIAL_STATE_PARITY; + if (temp & 0x0002) CDC_SerialState |= CDC_SERIAL_STATE_OVERRUN; + + return (CDC_SerialState); +} + + +/*---------------------------------------------------------------------------- + Send the SERIAL_STATE notification as defined in usbcdc11.pdf, 6.3.5. + *---------------------------------------------------------------------------*/ +void CDC_NotificationIn (void) { + + NotificationBuf[0] = 0xA1; // bmRequestType + NotificationBuf[1] = CDC_NOTIFICATION_SERIAL_STATE; // bNotification (SERIAL_STATE) + NotificationBuf[2] = 0x00; // wValue + NotificationBuf[3] = 0x00; + NotificationBuf[4] = 0x00; // wIndex (Interface #, LSB first) + NotificationBuf[5] = 0x00; + NotificationBuf[6] = 0x02; // wLength (Data length = 2 bytes, LSB first) + NotificationBuf[7] = 0x00; + NotificationBuf[8] = (CDC_SerialState >> 0) & 0xFF; // UART State Bitmap (16bits, LSB first) + NotificationBuf[9] = (CDC_SerialState >> 8) & 0xFF; + + USB_WriteEP (CDC_CEP_IN, &NotificationBuf[0], 10); // send notification +} diff --git a/firmware/usbcomp_msd_cdc/src/clkconfig.c b/firmware/usbcomp_msd_cdc/src/clkconfig.c index 8107b7d..346a83e 100644 --- a/firmware/usbcomp_msd_cdc/src/clkconfig.c +++ b/firmware/usbcomp_msd_cdc/src/clkconfig.c @@ -1,60 +1,60 @@ -/****************************************************************************** - * clkconfig.c: clock configuration C file for NXP LPC13xx Family - * Microprocessors - * - * Copyright(C) 2009, NXP Semiconductor - * All rights reserved. - * - * History - * 2009.08.20 ver 1.00 Preliminary version, first Release - * -******************************************************************************/ -#include "LPC13xx.h" -#include "clkconfig.h" - -/***************************************************************************** -** Function name: WDT_CLK_Setup -** -** Descriptions: Configure WDT clock. -** parameters: clock source: irc_osc(0), main_clk(1), wdt_osc(2). -** -** Returned value: None -** -*****************************************************************************/ -void WDT_CLK_Setup ( uint32_t clksrc ) -{ - /* Watchdog configuration. */ - /* Freq = 0.5Mhz, div_sel is 0, divided by 2. WDT_OSC should be 250khz */ - LPC_SYSCON->WDTOSCCTRL = (0x1<<5)|0x00; - LPC_SYSCON->WDTCLKSEL = clksrc; /* Select clock source */ - LPC_SYSCON->WDTCLKUEN = 0x01; /* Update clock */ - LPC_SYSCON->WDTCLKUEN = 0x00; /* Toggle update register once */ - LPC_SYSCON->WDTCLKUEN = 0x01; - while ( !(LPC_SYSCON->WDTCLKUEN & 0x01) ); /* Wait until updated */ - LPC_SYSCON->WDTCLKDIV = 1; /* Divided by 1 */ - LPC_SYSCON->PDRUNCFG &= ~(0x1<<6); /* Let WDT clock run */ - return; -} - -/***************************************************************************** -** Function name: CLKOUT_Setup -** -** Descriptions: Configure CLKOUT for reference clock check. -** parameters: clock source: irc_osc(0), sys_osc(1), wdt_osc(2), -** main_clk(3). -** -** Returned value: None -** -*****************************************************************************/ -void CLKOUT_Setup ( uint32_t clksrc ) -{ - /* debug PLL after configuration. */ - LPC_SYSCON->CLKOUTCLKSEL = clksrc; /* Select Main clock */ - LPC_SYSCON->CLKOUTUEN = 0x01; /* Update clock */ - LPC_SYSCON->CLKOUTUEN = 0x00; /* Toggle update register once */ - LPC_SYSCON->CLKOUTUEN = 0x01; - while ( !(LPC_SYSCON->CLKOUTUEN & 0x01) ); /* Wait until updated */ - LPC_SYSCON->CLKOUTDIV = 1; /* Divided by 1 */ - return; -} - +/****************************************************************************** + * clkconfig.c: clock configuration C file for NXP LPC13xx Family + * Microprocessors + * + * Copyright(C) 2009, NXP Semiconductor + * All rights reserved. + * + * History + * 2009.08.20 ver 1.00 Preliminary version, first Release + * +******************************************************************************/ +#include "LPC13xx.h" +#include "clkconfig.h" + +/***************************************************************************** +** Function name: WDT_CLK_Setup +** +** Descriptions: Configure WDT clock. +** parameters: clock source: irc_osc(0), main_clk(1), wdt_osc(2). +** +** Returned value: None +** +*****************************************************************************/ +void WDT_CLK_Setup ( uint32_t clksrc ) +{ + /* Watchdog configuration. */ + /* Freq = 0.5Mhz, div_sel is 0, divided by 2. WDT_OSC should be 250khz */ + LPC_SYSCON->WDTOSCCTRL = (0x1<<5)|0x00; + LPC_SYSCON->WDTCLKSEL = clksrc; /* Select clock source */ + LPC_SYSCON->WDTCLKUEN = 0x01; /* Update clock */ + LPC_SYSCON->WDTCLKUEN = 0x00; /* Toggle update register once */ + LPC_SYSCON->WDTCLKUEN = 0x01; + while ( !(LPC_SYSCON->WDTCLKUEN & 0x01) ); /* Wait until updated */ + LPC_SYSCON->WDTCLKDIV = 1; /* Divided by 1 */ + LPC_SYSCON->PDRUNCFG &= ~(0x1<<6); /* Let WDT clock run */ + return; +} + +/***************************************************************************** +** Function name: CLKOUT_Setup +** +** Descriptions: Configure CLKOUT for reference clock check. +** parameters: clock source: irc_osc(0), sys_osc(1), wdt_osc(2), +** main_clk(3). +** +** Returned value: None +** +*****************************************************************************/ +void CLKOUT_Setup ( uint32_t clksrc ) +{ + /* debug PLL after configuration. */ + LPC_SYSCON->CLKOUTCLKSEL = clksrc; /* Select Main clock */ + LPC_SYSCON->CLKOUTUEN = 0x01; /* Update clock */ + LPC_SYSCON->CLKOUTUEN = 0x00; /* Toggle update register once */ + LPC_SYSCON->CLKOUTUEN = 0x01; + while ( !(LPC_SYSCON->CLKOUTUEN & 0x01) ); /* Wait until updated */ + LPC_SYSCON->CLKOUTDIV = 1; /* Divided by 1 */ + return; +} + diff --git a/firmware/usbcomp_msd_cdc/src/cr_startup_lpc13.c b/firmware/usbcomp_msd_cdc/src/cr_startup_lpc13.c index a749437..89e42a3 100644 --- a/firmware/usbcomp_msd_cdc/src/cr_startup_lpc13.c +++ b/firmware/usbcomp_msd_cdc/src/cr_startup_lpc13.c @@ -1,359 +1,359 @@ -//***************************************************************************** -// +--+ -// | ++----+ -// +-++ | -// | | -// +-+--+ | -// | +--+--+ -// +----+ Copyright (c) 2009 Code Red Technologies Ltd. -// -// Microcontroller Startup code for use with Red Suite -// -// Software License Agreement -// -// The software is owned by Code Red Technologies and/or its suppliers, and is -// protected under applicable copyright laws. All rights are reserved. Any -// use in violation of the foregoing restrictions may subject the user to criminal -// sanctions under applicable laws, as well as to civil liability for the breach -// of the terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT -// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH -// CODE RED TECHNOLOGIES LTD. -// -//***************************************************************************** -#define WEAK __attribute__ ((weak)) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) - -// Code Red - if CMSIS is being used, then SystemInit() routine -// will be called by startup code rather than in application's main() -#ifdef __USE_CMSIS -#include "system_LPC13xx.h" -#endif - -//***************************************************************************** -// -// Forward declaration of the default handlers. These are aliased. -// When the application defines a handler (with the same name), this will -// automatically take precedence over these weak definitions -// -//***************************************************************************** - void Reset_Handler(void); - void ResetISR(void) ALIAS(Reset_Handler); -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -WEAK void MemManage_Handler(void); -WEAK void BusFault_Handler(void); -WEAK void UsageFault_Handler(void); -WEAK void SVCall_Handler(void); -WEAK void DebugMon_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); - -//***************************************************************************** -// -// Forward declaration of the specific IRQ handlers. These are aliased -// to the IntDefaultHandler, which is a 'forever' loop. When the application -// defines a handler (with the same name), this will automatically take -// precedence over these weak definitions -// -//***************************************************************************** - -void I2C_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler); -void SSP_IRQHandler (void) ALIAS(IntDefaultHandler); -void UART_IRQHandler (void) ALIAS(IntDefaultHandler); -void USB_IRQHandler (void) ALIAS(IntDefaultHandler); -void USB_FIQHandler (void) ALIAS(IntDefaultHandler); -void ADC_IRQHandler (void) ALIAS(IntDefaultHandler); -void WDT_IRQHandler (void) ALIAS(IntDefaultHandler); -void BOD_IRQHandler (void) ALIAS(IntDefaultHandler); -void FMC_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIOINT3_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIOINT2_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIOINT1_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIOINT0_IRQHandler (void) ALIAS(IntDefaultHandler); -void WAKEUP_IRQHandler (void) ALIAS(IntDefaultHandler); - -//***************************************************************************** -// -// The entry point for the application. -// __main() is the entry point for redlib based applications -// main() is the entry point for newlib based applications -// -//***************************************************************************** -extern WEAK void __main(void); -extern WEAK void main(void); -//***************************************************************************** -// -// External declaration for the pointer to the stack top from the Linker Script -// -//***************************************************************************** -extern void _vStackTop; - -//***************************************************************************** -// -// The vector table. Note that the proper constructs must be placed on this to -// ensure that it ends up at physical address 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - // Core Level - CM3 - (void *)&_vStackTop, // The initial stack pointer - Reset_Handler, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVCall_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - - - // Wakeup sources (40 ea.) for the I/O pins: - // PIO0 (0:11) - // PIO1 (0:11) - // PIO2 (0:11) - // PIO3 (0:3) - WAKEUP_IRQHandler, // PIO0_0 Wakeup - WAKEUP_IRQHandler, // PIO0_1 Wakeup - WAKEUP_IRQHandler, // PIO0_2 Wakeup - WAKEUP_IRQHandler, // PIO0_3 Wakeup - WAKEUP_IRQHandler, // PIO0_4 Wakeup - WAKEUP_IRQHandler, // PIO0_5 Wakeup - WAKEUP_IRQHandler, // PIO0_6 Wakeup - WAKEUP_IRQHandler, // PIO0_7 Wakeup - WAKEUP_IRQHandler, // PIO0_8 Wakeup - WAKEUP_IRQHandler, // PIO0_9 Wakeup - WAKEUP_IRQHandler, // PIO0_10 Wakeup - WAKEUP_IRQHandler, // PIO0_11 Wakeup - - WAKEUP_IRQHandler, // PIO1_0 Wakeup - WAKEUP_IRQHandler, // PIO1_1 Wakeup - WAKEUP_IRQHandler, // PIO1_2 Wakeup - WAKEUP_IRQHandler, // PIO1_3 Wakeup - WAKEUP_IRQHandler, // PIO1_4 Wakeup - WAKEUP_IRQHandler, // PIO1_5 Wakeup - WAKEUP_IRQHandler, // PIO1_6 Wakeup - WAKEUP_IRQHandler, // PIO1_7 Wakeup - WAKEUP_IRQHandler, // PIO1_8 Wakeup - WAKEUP_IRQHandler, // PIO1_9 Wakeup - WAKEUP_IRQHandler, // PIO1_10 Wakeup - WAKEUP_IRQHandler, // PIO1_11 Wakeup - - WAKEUP_IRQHandler, // PIO2_0 Wakeup - WAKEUP_IRQHandler, // PIO2_1 Wakeup - WAKEUP_IRQHandler, // PIO2_2 Wakeup - WAKEUP_IRQHandler, // PIO2_3 Wakeup - WAKEUP_IRQHandler, // PIO2_4 Wakeup - WAKEUP_IRQHandler, // PIO2_5 Wakeup - WAKEUP_IRQHandler, // PIO2_6 Wakeup - WAKEUP_IRQHandler, // PIO2_7 Wakeup - WAKEUP_IRQHandler, // PIO2_8 Wakeup - WAKEUP_IRQHandler, // PIO2_9 Wakeup - WAKEUP_IRQHandler, // PIO2_10 Wakeup - WAKEUP_IRQHandler, // PIO2_11 Wakeup - - WAKEUP_IRQHandler, // PIO3_0 Wakeup - WAKEUP_IRQHandler, // PIO3_1 Wakeup - WAKEUP_IRQHandler, // PIO3_2 Wakeup - WAKEUP_IRQHandler, // PIO3_3 Wakeup - - I2C_IRQHandler, // I2C0 - TIMER16_0_IRQHandler, // CT16B0 (16-bit Timer 0) - TIMER16_1_IRQHandler, // CT16B1 (16-bit Timer 1) - TIMER32_0_IRQHandler, // CT32B0 (32-bit Timer 0) - TIMER32_1_IRQHandler, // CT32B1 (32-bit Timer 1) - SSP_IRQHandler, // SSP0 - UART_IRQHandler, // UART0 - - USB_IRQHandler, // USB IRQ - USB_FIQHandler, // USB FIQ - - ADC_IRQHandler, // ADC (A/D Converter) - WDT_IRQHandler, // WDT (Watchdog Timer) - BOD_IRQHandler, // BOD (Brownout Detect) - FMC_IRQHandler, // Flash (IP2111 Flash Memory Controller) - PIOINT3_IRQHandler, // PIO INT3 - PIOINT2_IRQHandler, // PIO INT2 - PIOINT1_IRQHandler, // PIO INT1 - PIOINT0_IRQHandler, // PIO INT0 - -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern unsigned long _etext; -extern unsigned long _data; -extern unsigned long _edata; -extern unsigned long _bss; -extern unsigned long _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -//ResetISR(void) -Reset_Handler(void) -{ - unsigned long *pulSrc, *pulDest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = &_etext; - for(pulDest = &_data; pulDest < &_edata; ) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. This is done with inline assembly since this - // will clear the value of pulDest if it is not kept in a register. - // - __asm(" ldr r0, =_bss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); - -#ifdef __USE_CMSIS - SystemInit(); -#endif - - // - // Call the application's entry point. - // __main() is the entry point for redlib based applications (which calls main()) - // main() is the entry point for newlib based applications - // - if (__main) - __main() ; - else - main() ; - - // - // main() shouldn't return, but if it does, we'll just enter an infinite loop - // - while (1) { - ; - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -void NMI_Handler(void) -{ - while(1) - { - } -} - -void HardFault_Handler(void) -{ - while(1) - { - } -} - -void MemManage_Handler(void) -{ - while(1) - { - } -} - -void BusFault_Handler(void) -{ - while(1) - { - } -} - -void UsageFault_Handler(void) -{ - while(1) - { - } -} - -void SVCall_Handler(void) -{ - while(1) - { - } -} - -void DebugMon_Handler(void) -{ - while(1) - { - } -} - -void PendSV_Handler(void) -{ - while(1) - { - } -} - -void SysTick_Handler(void) -{ - while(1) - { - } -} - -//***************************************************************************** -// -// Processor ends up here if an unexpected interrupt occurs or a handler -// is not present in the application code. -// -//***************************************************************************** - -static void IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} +//***************************************************************************** +// +--+ +// | ++----+ +// +-++ | +// | | +// +-+--+ | +// | +--+--+ +// +----+ Copyright (c) 2009 Code Red Technologies Ltd. +// +// Microcontroller Startup code for use with Red Suite +// +// Software License Agreement +// +// The software is owned by Code Red Technologies and/or its suppliers, and is +// protected under applicable copyright laws. All rights are reserved. Any +// use in violation of the foregoing restrictions may subject the user to criminal +// sanctions under applicable laws, as well as to civil liability for the breach +// of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT +// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH +// CODE RED TECHNOLOGIES LTD. +// +//***************************************************************************** +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +// Code Red - if CMSIS is being used, then SystemInit() routine +// will be called by startup code rather than in application's main() +#ifdef __USE_CMSIS +#include "system_LPC13xx.h" +#endif + +//***************************************************************************** +// +// Forward declaration of the default handlers. These are aliased. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions +// +//***************************************************************************** + void Reset_Handler(void); + void ResetISR(void) ALIAS(Reset_Handler); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SVCall_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); + +//***************************************************************************** +// +// Forward declaration of the specific IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the application +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +// +//***************************************************************************** + +void I2C_IRQHandler (void) ALIAS(IntDefaultHandler); +void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler); +void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler); +void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler); +void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler); +void SSP_IRQHandler (void) ALIAS(IntDefaultHandler); +void UART_IRQHandler (void) ALIAS(IntDefaultHandler); +void USB_IRQHandler (void) ALIAS(IntDefaultHandler); +void USB_FIQHandler (void) ALIAS(IntDefaultHandler); +void ADC_IRQHandler (void) ALIAS(IntDefaultHandler); +void WDT_IRQHandler (void) ALIAS(IntDefaultHandler); +void BOD_IRQHandler (void) ALIAS(IntDefaultHandler); +void FMC_IRQHandler (void) ALIAS(IntDefaultHandler); +void PIOINT3_IRQHandler (void) ALIAS(IntDefaultHandler); +void PIOINT2_IRQHandler (void) ALIAS(IntDefaultHandler); +void PIOINT1_IRQHandler (void) ALIAS(IntDefaultHandler); +void PIOINT0_IRQHandler (void) ALIAS(IntDefaultHandler); +void WAKEUP_IRQHandler (void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// +// The entry point for the application. +// __main() is the entry point for redlib based applications +// main() is the entry point for newlib based applications +// +//***************************************************************************** +extern WEAK void __main(void); +extern WEAK void main(void); +//***************************************************************************** +// +// External declaration for the pointer to the stack top from the Linker Script +// +//***************************************************************************** +extern void _vStackTop; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + // Core Level - CM3 + (void *)&_vStackTop, // The initial stack pointer + Reset_Handler, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVCall_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + + + // Wakeup sources (40 ea.) for the I/O pins: + // PIO0 (0:11) + // PIO1 (0:11) + // PIO2 (0:11) + // PIO3 (0:3) + WAKEUP_IRQHandler, // PIO0_0 Wakeup + WAKEUP_IRQHandler, // PIO0_1 Wakeup + WAKEUP_IRQHandler, // PIO0_2 Wakeup + WAKEUP_IRQHandler, // PIO0_3 Wakeup + WAKEUP_IRQHandler, // PIO0_4 Wakeup + WAKEUP_IRQHandler, // PIO0_5 Wakeup + WAKEUP_IRQHandler, // PIO0_6 Wakeup + WAKEUP_IRQHandler, // PIO0_7 Wakeup + WAKEUP_IRQHandler, // PIO0_8 Wakeup + WAKEUP_IRQHandler, // PIO0_9 Wakeup + WAKEUP_IRQHandler, // PIO0_10 Wakeup + WAKEUP_IRQHandler, // PIO0_11 Wakeup + + WAKEUP_IRQHandler, // PIO1_0 Wakeup + WAKEUP_IRQHandler, // PIO1_1 Wakeup + WAKEUP_IRQHandler, // PIO1_2 Wakeup + WAKEUP_IRQHandler, // PIO1_3 Wakeup + WAKEUP_IRQHandler, // PIO1_4 Wakeup + WAKEUP_IRQHandler, // PIO1_5 Wakeup + WAKEUP_IRQHandler, // PIO1_6 Wakeup + WAKEUP_IRQHandler, // PIO1_7 Wakeup + WAKEUP_IRQHandler, // PIO1_8 Wakeup + WAKEUP_IRQHandler, // PIO1_9 Wakeup + WAKEUP_IRQHandler, // PIO1_10 Wakeup + WAKEUP_IRQHandler, // PIO1_11 Wakeup + + WAKEUP_IRQHandler, // PIO2_0 Wakeup + WAKEUP_IRQHandler, // PIO2_1 Wakeup + WAKEUP_IRQHandler, // PIO2_2 Wakeup + WAKEUP_IRQHandler, // PIO2_3 Wakeup + WAKEUP_IRQHandler, // PIO2_4 Wakeup + WAKEUP_IRQHandler, // PIO2_5 Wakeup + WAKEUP_IRQHandler, // PIO2_6 Wakeup + WAKEUP_IRQHandler, // PIO2_7 Wakeup + WAKEUP_IRQHandler, // PIO2_8 Wakeup + WAKEUP_IRQHandler, // PIO2_9 Wakeup + WAKEUP_IRQHandler, // PIO2_10 Wakeup + WAKEUP_IRQHandler, // PIO2_11 Wakeup + + WAKEUP_IRQHandler, // PIO3_0 Wakeup + WAKEUP_IRQHandler, // PIO3_1 Wakeup + WAKEUP_IRQHandler, // PIO3_2 Wakeup + WAKEUP_IRQHandler, // PIO3_3 Wakeup + + I2C_IRQHandler, // I2C0 + TIMER16_0_IRQHandler, // CT16B0 (16-bit Timer 0) + TIMER16_1_IRQHandler, // CT16B1 (16-bit Timer 1) + TIMER32_0_IRQHandler, // CT32B0 (32-bit Timer 0) + TIMER32_1_IRQHandler, // CT32B1 (32-bit Timer 1) + SSP_IRQHandler, // SSP0 + UART_IRQHandler, // UART0 + + USB_IRQHandler, // USB IRQ + USB_FIQHandler, // USB FIQ + + ADC_IRQHandler, // ADC (A/D Converter) + WDT_IRQHandler, // WDT (Watchdog Timer) + BOD_IRQHandler, // BOD (Brownout Detect) + FMC_IRQHandler, // Flash (IP2111 Flash Memory Controller) + PIOINT3_IRQHandler, // PIO INT3 + PIOINT2_IRQHandler, // PIO INT2 + PIOINT1_IRQHandler, // PIO INT1 + PIOINT0_IRQHandler, // PIO INT0 + +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +//ResetISR(void) +Reset_Handler(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. This is done with inline assembly since this + // will clear the value of pulDest if it is not kept in a register. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + +#ifdef __USE_CMSIS + SystemInit(); +#endif + + // + // Call the application's entry point. + // __main() is the entry point for redlib based applications (which calls main()) + // main() is the entry point for newlib based applications + // + if (__main) + __main() ; + else + main() ; + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +void NMI_Handler(void) +{ + while(1) + { + } +} + +void HardFault_Handler(void) +{ + while(1) + { + } +} + +void MemManage_Handler(void) +{ + while(1) + { + } +} + +void BusFault_Handler(void) +{ + while(1) + { + } +} + +void UsageFault_Handler(void) +{ + while(1) + { + } +} + +void SVCall_Handler(void) +{ + while(1) + { + } +} + +void DebugMon_Handler(void) +{ + while(1) + { + } +} + +void PendSV_Handler(void) +{ + while(1) + { + } +} + +void SysTick_Handler(void) +{ + while(1) + { + } +} + +//***************************************************************************** +// +// Processor ends up here if an unexpected interrupt occurs or a handler +// is not present in the application code. +// +//***************************************************************************** + +static void IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/firmware/usbcomp_msd_cdc/src/mscuser.c b/firmware/usbcomp_msd_cdc/src/mscuser.c index 00d0752..009e199 100644 --- a/firmware/usbcomp_msd_cdc/src/mscuser.c +++ b/firmware/usbcomp_msd_cdc/src/mscuser.c @@ -1,708 +1,708 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: mscuser.c - * Purpose: Mass Storage Class Custom User Module - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added SCSI_READ12, SCSI_WRITE12 - * V1.00 Initial Version - *---------------------------------------------------------------------------*/ -#include "type.h" - -#include "usb.h" -#include "msc.h" -#include "usbcfg.h" -#include "usbhw.h" -#include "usbcore.h" -#include "mscuser.h" -#include "memory.h" - - -uint8_t Memory[MSC_MemorySize]; /* MSC RAM */ - -uint32_t MemOK; /* Memory OK */ - -uint32_t Offset; /* R/W Offset */ -uint32_t Length; /* R/W Length */ - -uint8_t BulkStage = MSC_BS_CBW; /* Bulk Stage */ - -uint8_t BulkBuf[MSC_MAX_PACKET] __attribute__ ((aligned (4))); /* Bulk In/Out Buffer */ -uint8_t BulkLen; /* Bulk In/Out Length */ - -MSC_CBW CBW; /* Command Block Wrapper */ -MSC_CSW CSW; /* Command Status Wrapper */ - - - -/* - * Set Stall for MSC Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void MSC_SetStallEP (uint32_t EPNum) { /* set EP halt status according stall status */ - USB_SetStallEP(EPNum); - USB_EndPointHalt |= (EPNum & 0x80) ? ((1 << 16) << (EPNum & 0x0F)) : (1 << EPNum); -} - - -/* - * MSC Mass Storage Reset Request Callback - * Called automatically on Mass Storage Reset Request - * Parameters: None (global SetupPacket and EP0Buf) - * Return Value: TRUE - Success, FALSE - Error - */ - -uint32_t MSC_Reset (void) { - - - USB_EndPointStall = 0x00000000; /* EP must stay stalled */ - CSW.dSignature = 0; /* invalid signature */ - - BulkStage = MSC_BS_CBW; - - return (TRUE); -} - - -/* - * MSC Get Max LUN Request Callback - * Called automatically on Get Max LUN Request - * Parameters: None (global SetupPacket and EP0Buf) - * Return Value: TRUE - Success, FALSE - Error - */ - -uint32_t MSC_GetMaxLUN (void) { - - EP0Buf[0] = 0; /* No LUN associated with this device */ - return (TRUE); -} - - -/* - * MSC Memory Read Callback - * Called automatically on Memory Read Event - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_MemoryRead (void) { - uint32_t n; - - if (Length > MSC_MAX_PACKET) { - n = MSC_MAX_PACKET; - } else { - n = Length; - } - - if ((Offset + n) > MSC_MemorySize) { - n = MSC_MemorySize - Offset; - BulkStage = MSC_BS_DATA_IN_LAST_STALL; - } - - USB_WriteEP(MSC_EP_IN, &Memory[Offset], n); - Offset += n; - Length -= n; - - CSW.dDataResidue -= n; - - if (Length == 0) { - BulkStage = MSC_BS_DATA_IN_LAST; - } - - if (BulkStage != MSC_BS_DATA_IN) { - CSW.bStatus = CSW_CMD_PASSED; - } -} - - -/* - * MSC Memory Write Callback - * Called automatically on Memory Write Event - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_MemoryWrite (void) { - uint32_t n; - - if ((Offset + BulkLen) > MSC_MemorySize) { - BulkLen = MSC_MemorySize - Offset; - BulkStage = MSC_BS_CSW; - MSC_SetStallEP(MSC_EP_OUT); - } - - for (n = 0; n < BulkLen; n++) { - Memory[Offset + n] = BulkBuf[n]; - } - - Offset += BulkLen; - Length -= BulkLen; - - CSW.dDataResidue -= BulkLen; - - if ((Length == 0) || (BulkStage == MSC_BS_CSW)) { - CSW.bStatus = CSW_CMD_PASSED; - MSC_SetCSW(); - } -} - - -/* - * MSC Memory Verify Callback - * Called automatically on Memory Verify Event - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_MemoryVerify (void) { - uint32_t n; - - if ((Offset + BulkLen) > MSC_MemorySize) { - BulkLen = MSC_MemorySize - Offset; - BulkStage = MSC_BS_CSW; - MSC_SetStallEP(MSC_EP_OUT); - } - - for (n = 0; n < BulkLen; n++) { - if (Memory[Offset + n] != BulkBuf[n]) { - MemOK = FALSE; - break; - } - } - - Offset += BulkLen; - Length -= BulkLen; - - CSW.dDataResidue -= BulkLen; - - if ((Length == 0) || (BulkStage == MSC_BS_CSW)) { - CSW.bStatus = (MemOK) ? CSW_CMD_PASSED : CSW_CMD_FAILED; - MSC_SetCSW(); - } -} - - -/* - * MSC SCSI Read/Write Setup Callback - * Parameters: None (global variables) - * Return Value: TRUE - Success, FALSE - Error - */ - -uint32_t MSC_RWSetup (void) { - uint32_t n; - - /* Logical Block Address of First Block */ - n = (CBW.CB[2] << 24) | - (CBW.CB[3] << 16) | - (CBW.CB[4] << 8) | - (CBW.CB[5] << 0); - - Offset = n * MSC_BlockSize; - - /* Number of Blocks to transfer */ - switch (CBW.CB[0]) { - case SCSI_READ10: - case SCSI_WRITE10: - case SCSI_VERIFY10: - n = (CBW.CB[7] << 8) | - (CBW.CB[8] << 0); - break; - - case SCSI_READ12: - case SCSI_WRITE12: - n = (CBW.CB[6] << 24) | - (CBW.CB[7] << 16) | - (CBW.CB[8] << 8) | - (CBW.CB[9] << 0); - break; - } - - Length = n * MSC_BlockSize; - - if (CBW.dDataLength == 0) { /* host requests no data */ - CSW.bStatus = CSW_CMD_FAILED; - MSC_SetCSW(); - return (FALSE); - } - - if (CBW.dDataLength != Length) { - if ((CBW.bmFlags & 0x80) != 0) { /* stall appropriate EP */ - MSC_SetStallEP(MSC_EP_IN); - } else { - MSC_SetStallEP(MSC_EP_OUT); - } - - CSW.bStatus = CSW_CMD_FAILED; - MSC_SetCSW(); - - return (FALSE); - } - - return (TRUE); -} - - -/* - * Check Data IN Format - * Parameters: None (global variables) - * Return Value: TRUE - Success, FALSE - Error - */ - -uint32_t DataInFormat (void) { - - if (CBW.dDataLength == 0) { - CSW.bStatus = CSW_PHASE_ERROR; - MSC_SetCSW(); - return (FALSE); - } - if ((CBW.bmFlags & 0x80) == 0) { - MSC_SetStallEP(MSC_EP_OUT); - CSW.bStatus = CSW_PHASE_ERROR; - MSC_SetCSW(); - return (FALSE); - } - return (TRUE); -} - - -/* - * Perform Data IN Transfer - * Parameters: None (global variables) - * Return Value: TRUE - Success, FALSE - Error - */ - -void DataInTransfer (void) { - - if (BulkLen >= CBW.dDataLength) - BulkLen = CBW.dDataLength; - - BulkStage = MSC_BS_DATA_IN_LAST; - - USB_WriteEP(MSC_EP_IN, BulkBuf, BulkLen); - - CSW.dDataResidue -= BulkLen; - CSW.bStatus = CSW_CMD_PASSED; -} - - -/* - * MSC SCSI Test Unit Ready Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_TestUnitReady (void) { - - if (CBW.dDataLength != 0) { - if ((CBW.bmFlags & 0x80) != 0) { - MSC_SetStallEP(MSC_EP_IN); - } else { - MSC_SetStallEP(MSC_EP_OUT); - } - } - - CSW.bStatus = CSW_CMD_PASSED; - MSC_SetCSW(); -} - - -/* - * MSC SCSI Request Sense Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_RequestSense (void) { - - if (!DataInFormat()) return; - - BulkBuf[ 0] = 0x70; /* Response Code */ - BulkBuf[ 1] = 0x00; - BulkBuf[ 2] = 0x02; /* Sense Key */ - BulkBuf[ 3] = 0x00; - BulkBuf[ 4] = 0x00; - BulkBuf[ 5] = 0x00; - BulkBuf[ 6] = 0x00; - BulkBuf[ 7] = 0x0A; /* Additional Length */ - BulkBuf[ 8] = 0x00; - BulkBuf[ 9] = 0x00; - BulkBuf[10] = 0x00; - BulkBuf[11] = 0x00; - BulkBuf[12] = 0x30; /* ASC */ - BulkBuf[13] = 0x01; /* ASCQ */ - BulkBuf[14] = 0x00; - BulkBuf[15] = 0x00; - BulkBuf[16] = 0x00; - BulkBuf[17] = 0x00; - - BulkLen = 18; - DataInTransfer(); -} - - -/* - * MSC SCSI Inquiry Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_Inquiry (void) { - - if (!DataInFormat()) return; - - BulkBuf[ 0] = 0x00; /* Direct Access Device */ - BulkBuf[ 1] = 0x80; /* RMB = 1: Removable Medium */ - BulkBuf[ 2] = 0x00; /* Version: No conformance claim to standard */ - BulkBuf[ 3] = 0x01; - - BulkBuf[ 4] = 36-4; /* Additional Length */ - BulkBuf[ 5] = 0x80; /* SCCS = 1: Storage Controller Component */ - BulkBuf[ 6] = 0x00; - BulkBuf[ 7] = 0x00; - - BulkBuf[ 8] = 'K'; /* Vendor Identification */ - BulkBuf[ 9] = 'e'; - BulkBuf[10] = 'i'; - BulkBuf[11] = 'l'; - BulkBuf[12] = ' '; - BulkBuf[13] = ' '; - BulkBuf[14] = ' '; - BulkBuf[15] = ' '; - - BulkBuf[16] = 'L'; /* Product Identification */ - BulkBuf[17] = 'P'; - BulkBuf[18] = 'C'; - BulkBuf[19] = '1'; - BulkBuf[20] = '3'; - BulkBuf[21] = '4'; - BulkBuf[22] = 'x'; - BulkBuf[23] = ' '; - BulkBuf[24] = 'D'; - BulkBuf[25] = 'i'; - BulkBuf[26] = 's'; - BulkBuf[27] = 'k'; - BulkBuf[28] = ' '; - BulkBuf[29] = ' '; - BulkBuf[30] = ' '; - BulkBuf[31] = ' '; - - BulkBuf[32] = '1'; /* Product Revision Level */ - BulkBuf[33] = '.'; - BulkBuf[34] = '0'; - BulkBuf[35] = ' '; - - BulkLen = 36; - DataInTransfer(); -} - - -/* - * MSC SCSI Mode Sense (6-Byte) Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_ModeSense6 (void) { - - if (!DataInFormat()) return; - - BulkBuf[ 0] = 0x03; - BulkBuf[ 1] = 0x00; - BulkBuf[ 2] = 0x00; - BulkBuf[ 3] = 0x00; - - BulkLen = 4; - DataInTransfer(); -} - - -/* - * MSC SCSI Mode Sense (10-Byte) Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_ModeSense10 (void) { - - if (!DataInFormat()) return; - - BulkBuf[ 0] = 0x00; - BulkBuf[ 1] = 0x06; - BulkBuf[ 2] = 0x00; - BulkBuf[ 3] = 0x00; - BulkBuf[ 4] = 0x00; - BulkBuf[ 5] = 0x00; - BulkBuf[ 6] = 0x00; - BulkBuf[ 7] = 0x00; - - BulkLen = 8; - DataInTransfer(); -} - - -/* - * MSC SCSI Read Capacity Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_ReadCapacity (void) { - - if (!DataInFormat()) return; - - /* Last Logical Block */ - BulkBuf[ 0] = ((MSC_BlockCount - 1) >> 24) & 0xFF; - BulkBuf[ 1] = ((MSC_BlockCount - 1) >> 16) & 0xFF; - BulkBuf[ 2] = ((MSC_BlockCount - 1) >> 8) & 0xFF; - BulkBuf[ 3] = ((MSC_BlockCount - 1) >> 0) & 0xFF; - - /* Block Length */ - BulkBuf[ 4] = (MSC_BlockSize >> 24) & 0xFF; - BulkBuf[ 5] = (MSC_BlockSize >> 16) & 0xFF; - BulkBuf[ 6] = (MSC_BlockSize >> 8) & 0xFF; - BulkBuf[ 7] = (MSC_BlockSize >> 0) & 0xFF; - - BulkLen = 8; - DataInTransfer(); -} - - -/* - * MSC SCSI Read Format Capacity Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_ReadFormatCapacity (void) { - - if (!DataInFormat()) return; - - BulkBuf[ 0] = 0x00; - BulkBuf[ 1] = 0x00; - BulkBuf[ 2] = 0x00; - BulkBuf[ 3] = 0x08; /* Capacity List Length */ - - /* Block Count */ - BulkBuf[ 4] = (MSC_BlockCount >> 24) & 0xFF; - BulkBuf[ 5] = (MSC_BlockCount >> 16) & 0xFF; - BulkBuf[ 6] = (MSC_BlockCount >> 8) & 0xFF; - BulkBuf[ 7] = (MSC_BlockCount >> 0) & 0xFF; - - /* Block Length */ - BulkBuf[ 8] = 0x02; /* Descriptor Code: Formatted Media */ - BulkBuf[ 9] = (MSC_BlockSize >> 16) & 0xFF; - BulkBuf[10] = (MSC_BlockSize >> 8) & 0xFF; - BulkBuf[11] = (MSC_BlockSize >> 0) & 0xFF; - - BulkLen = 12; - DataInTransfer(); -} - - -/* - * MSC Get Command Block Wrapper Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_GetCBW (void) { - uint32_t n; - - for (n = 0; n < BulkLen; n++) { - *((uint8_t *)&CBW + n) = BulkBuf[n]; - } - if ((BulkLen == sizeof(CBW)) && (CBW.dSignature == MSC_CBW_Signature)) { - /* Valid CBW */ - CSW.dTag = CBW.dTag; - CSW.dDataResidue = CBW.dDataLength; - if ((CBW.bLUN != 0) || - (CBW.bCBLength < 1) || - (CBW.bCBLength > 16) ) { -fail: - CSW.bStatus = CSW_CMD_FAILED; - MSC_SetCSW(); - } else { - switch (CBW.CB[0]) { - case SCSI_TEST_UNIT_READY: - MSC_TestUnitReady(); - break; - case SCSI_REQUEST_SENSE: - MSC_RequestSense(); - break; - case SCSI_FORMAT_UNIT: - goto fail; - case SCSI_INQUIRY: - MSC_Inquiry(); - break; - case SCSI_START_STOP_UNIT: - goto fail; - case SCSI_MEDIA_REMOVAL: - goto fail; - case SCSI_MODE_SELECT6: - goto fail; - case SCSI_MODE_SENSE6: - MSC_ModeSense6(); - break; - case SCSI_MODE_SELECT10: - goto fail; - case SCSI_MODE_SENSE10: - MSC_ModeSense10(); - break; - case SCSI_READ_FORMAT_CAPACITIES: - MSC_ReadFormatCapacity(); - break; - case SCSI_READ_CAPACITY: - MSC_ReadCapacity(); - break; - case SCSI_READ10: - case SCSI_READ12: - if (MSC_RWSetup()) { - if ((CBW.bmFlags & 0x80) != 0) { - BulkStage = MSC_BS_DATA_IN; - MSC_MemoryRead(); - } else { /* direction mismatch */ - MSC_SetStallEP(MSC_EP_OUT); - CSW.bStatus = CSW_PHASE_ERROR; - MSC_SetCSW(); - } - } - break; - case SCSI_WRITE10: - case SCSI_WRITE12: - if (MSC_RWSetup()) { - if ((CBW.bmFlags & 0x80) == 0) { - BulkStage = MSC_BS_DATA_OUT; - } else { /* direction mismatch */ - MSC_SetStallEP(MSC_EP_IN); - CSW.bStatus = CSW_PHASE_ERROR; - MSC_SetCSW(); - } - } - break; - case SCSI_VERIFY10: - if ((CBW.CB[1] & 0x02) == 0) { - // BYTCHK = 0 -> CRC Check (not implemented) - CSW.bStatus = CSW_CMD_PASSED; - MSC_SetCSW(); - break; - } - if (MSC_RWSetup()) { - if ((CBW.bmFlags & 0x80) == 0) { - BulkStage = MSC_BS_DATA_OUT; - MemOK = TRUE; - } else { - MSC_SetStallEP(MSC_EP_IN); - CSW.bStatus = CSW_PHASE_ERROR; - MSC_SetCSW(); - } - } - break; - default: - goto fail; - } - } - } else { - /* Invalid CBW */ - MSC_SetStallEP(MSC_EP_IN); - /* set EP to stay stalled */ - USB_EndPointStall |= (MSC_EP_IN & 0x80) ? ((1 << 16) << (MSC_EP_IN & 0x0F)) : (1 << MSC_EP_IN); - MSC_SetStallEP(MSC_EP_OUT); - /* set EP to stay stalled */ - USB_EndPointStall |= (MSC_EP_OUT & 0x80) ? ((1 << 16) << (MSC_EP_OUT & 0x0F)) : (1 << MSC_EP_OUT); - BulkStage = MSC_BS_ERROR; - } -} - - -/* - * MSC Set Command Status Wrapper Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_SetCSW (void) { - - CSW.dSignature = MSC_CSW_Signature; - USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW)); - BulkStage = MSC_BS_CSW; -} - - -/* - * MSC Bulk In Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_BulkIn (void) { - - switch (BulkStage) { - case MSC_BS_DATA_IN: - switch (CBW.CB[0]) { - case SCSI_READ10: - case SCSI_READ12: - MSC_MemoryRead(); - break; - } - break; - case MSC_BS_DATA_IN_LAST: - MSC_SetCSW(); - break; - case MSC_BS_DATA_IN_LAST_STALL: - MSC_SetStallEP(MSC_EP_IN); - MSC_SetCSW(); - break; - case MSC_BS_CSW: - BulkStage = MSC_BS_CBW; - break; - } -} - - -/* - * MSC Bulk Out Callback - * Parameters: None (global variables) - * Return Value: None - */ - -void MSC_BulkOut (void) { - - BulkLen = USB_ReadEP(MSC_EP_OUT, BulkBuf); - switch (BulkStage) { - case MSC_BS_CBW: - MSC_GetCBW(); - break; - case MSC_BS_DATA_OUT: - switch (CBW.CB[0]) { - case SCSI_WRITE10: - case SCSI_WRITE12: - MSC_MemoryWrite(); - break; - case SCSI_VERIFY10: - MSC_MemoryVerify(); - break; - } - break; - default: - MSC_SetStallEP(MSC_EP_OUT); - CSW.bStatus = CSW_PHASE_ERROR; - MSC_SetCSW(); - break; - } -} +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: mscuser.c + * Purpose: Mass Storage Class Custom User Module + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------- + * History: + * V1.20 Added SCSI_READ12, SCSI_WRITE12 + * V1.00 Initial Version + *---------------------------------------------------------------------------*/ +#include "type.h" + +#include "usb.h" +#include "msc.h" +#include "usbcfg.h" +#include "usbhw.h" +#include "usbcore.h" +#include "mscuser.h" +#include "memory.h" + + +uint8_t Memory[MSC_MemorySize]; /* MSC RAM */ + +uint32_t MemOK; /* Memory OK */ + +uint32_t Offset; /* R/W Offset */ +uint32_t Length; /* R/W Length */ + +uint8_t BulkStage = MSC_BS_CBW; /* Bulk Stage */ + +uint8_t BulkBuf[MSC_MAX_PACKET] __attribute__ ((aligned (4))); /* Bulk In/Out Buffer */ +uint8_t BulkLen; /* Bulk In/Out Length */ + +MSC_CBW CBW; /* Command Block Wrapper */ +MSC_CSW CSW; /* Command Status Wrapper */ + + + +/* + * Set Stall for MSC Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void MSC_SetStallEP (uint32_t EPNum) { /* set EP halt status according stall status */ + USB_SetStallEP(EPNum); + USB_EndPointHalt |= (EPNum & 0x80) ? ((1 << 16) << (EPNum & 0x0F)) : (1 << EPNum); +} + + +/* + * MSC Mass Storage Reset Request Callback + * Called automatically on Mass Storage Reset Request + * Parameters: None (global SetupPacket and EP0Buf) + * Return Value: TRUE - Success, FALSE - Error + */ + +uint32_t MSC_Reset (void) { + + + USB_EndPointStall = 0x00000000; /* EP must stay stalled */ + CSW.dSignature = 0; /* invalid signature */ + + BulkStage = MSC_BS_CBW; + + return (TRUE); +} + + +/* + * MSC Get Max LUN Request Callback + * Called automatically on Get Max LUN Request + * Parameters: None (global SetupPacket and EP0Buf) + * Return Value: TRUE - Success, FALSE - Error + */ + +uint32_t MSC_GetMaxLUN (void) { + + EP0Buf[0] = 0; /* No LUN associated with this device */ + return (TRUE); +} + + +/* + * MSC Memory Read Callback + * Called automatically on Memory Read Event + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_MemoryRead (void) { + uint32_t n; + + if (Length > MSC_MAX_PACKET) { + n = MSC_MAX_PACKET; + } else { + n = Length; + } + + if ((Offset + n) > MSC_MemorySize) { + n = MSC_MemorySize - Offset; + BulkStage = MSC_BS_DATA_IN_LAST_STALL; + } + + USB_WriteEP(MSC_EP_IN, &Memory[Offset], n); + Offset += n; + Length -= n; + + CSW.dDataResidue -= n; + + if (Length == 0) { + BulkStage = MSC_BS_DATA_IN_LAST; + } + + if (BulkStage != MSC_BS_DATA_IN) { + CSW.bStatus = CSW_CMD_PASSED; + } +} + + +/* + * MSC Memory Write Callback + * Called automatically on Memory Write Event + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_MemoryWrite (void) { + uint32_t n; + + if ((Offset + BulkLen) > MSC_MemorySize) { + BulkLen = MSC_MemorySize - Offset; + BulkStage = MSC_BS_CSW; + MSC_SetStallEP(MSC_EP_OUT); + } + + for (n = 0; n < BulkLen; n++) { + Memory[Offset + n] = BulkBuf[n]; + } + + Offset += BulkLen; + Length -= BulkLen; + + CSW.dDataResidue -= BulkLen; + + if ((Length == 0) || (BulkStage == MSC_BS_CSW)) { + CSW.bStatus = CSW_CMD_PASSED; + MSC_SetCSW(); + } +} + + +/* + * MSC Memory Verify Callback + * Called automatically on Memory Verify Event + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_MemoryVerify (void) { + uint32_t n; + + if ((Offset + BulkLen) > MSC_MemorySize) { + BulkLen = MSC_MemorySize - Offset; + BulkStage = MSC_BS_CSW; + MSC_SetStallEP(MSC_EP_OUT); + } + + for (n = 0; n < BulkLen; n++) { + if (Memory[Offset + n] != BulkBuf[n]) { + MemOK = FALSE; + break; + } + } + + Offset += BulkLen; + Length -= BulkLen; + + CSW.dDataResidue -= BulkLen; + + if ((Length == 0) || (BulkStage == MSC_BS_CSW)) { + CSW.bStatus = (MemOK) ? CSW_CMD_PASSED : CSW_CMD_FAILED; + MSC_SetCSW(); + } +} + + +/* + * MSC SCSI Read/Write Setup Callback + * Parameters: None (global variables) + * Return Value: TRUE - Success, FALSE - Error + */ + +uint32_t MSC_RWSetup (void) { + uint32_t n; + + /* Logical Block Address of First Block */ + n = (CBW.CB[2] << 24) | + (CBW.CB[3] << 16) | + (CBW.CB[4] << 8) | + (CBW.CB[5] << 0); + + Offset = n * MSC_BlockSize; + + /* Number of Blocks to transfer */ + switch (CBW.CB[0]) { + case SCSI_READ10: + case SCSI_WRITE10: + case SCSI_VERIFY10: + n = (CBW.CB[7] << 8) | + (CBW.CB[8] << 0); + break; + + case SCSI_READ12: + case SCSI_WRITE12: + n = (CBW.CB[6] << 24) | + (CBW.CB[7] << 16) | + (CBW.CB[8] << 8) | + (CBW.CB[9] << 0); + break; + } + + Length = n * MSC_BlockSize; + + if (CBW.dDataLength == 0) { /* host requests no data */ + CSW.bStatus = CSW_CMD_FAILED; + MSC_SetCSW(); + return (FALSE); + } + + if (CBW.dDataLength != Length) { + if ((CBW.bmFlags & 0x80) != 0) { /* stall appropriate EP */ + MSC_SetStallEP(MSC_EP_IN); + } else { + MSC_SetStallEP(MSC_EP_OUT); + } + + CSW.bStatus = CSW_CMD_FAILED; + MSC_SetCSW(); + + return (FALSE); + } + + return (TRUE); +} + + +/* + * Check Data IN Format + * Parameters: None (global variables) + * Return Value: TRUE - Success, FALSE - Error + */ + +uint32_t DataInFormat (void) { + + if (CBW.dDataLength == 0) { + CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(); + return (FALSE); + } + if ((CBW.bmFlags & 0x80) == 0) { + MSC_SetStallEP(MSC_EP_OUT); + CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(); + return (FALSE); + } + return (TRUE); +} + + +/* + * Perform Data IN Transfer + * Parameters: None (global variables) + * Return Value: TRUE - Success, FALSE - Error + */ + +void DataInTransfer (void) { + + if (BulkLen >= CBW.dDataLength) + BulkLen = CBW.dDataLength; + + BulkStage = MSC_BS_DATA_IN_LAST; + + USB_WriteEP(MSC_EP_IN, BulkBuf, BulkLen); + + CSW.dDataResidue -= BulkLen; + CSW.bStatus = CSW_CMD_PASSED; +} + + +/* + * MSC SCSI Test Unit Ready Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_TestUnitReady (void) { + + if (CBW.dDataLength != 0) { + if ((CBW.bmFlags & 0x80) != 0) { + MSC_SetStallEP(MSC_EP_IN); + } else { + MSC_SetStallEP(MSC_EP_OUT); + } + } + + CSW.bStatus = CSW_CMD_PASSED; + MSC_SetCSW(); +} + + +/* + * MSC SCSI Request Sense Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_RequestSense (void) { + + if (!DataInFormat()) return; + + BulkBuf[ 0] = 0x70; /* Response Code */ + BulkBuf[ 1] = 0x00; + BulkBuf[ 2] = 0x02; /* Sense Key */ + BulkBuf[ 3] = 0x00; + BulkBuf[ 4] = 0x00; + BulkBuf[ 5] = 0x00; + BulkBuf[ 6] = 0x00; + BulkBuf[ 7] = 0x0A; /* Additional Length */ + BulkBuf[ 8] = 0x00; + BulkBuf[ 9] = 0x00; + BulkBuf[10] = 0x00; + BulkBuf[11] = 0x00; + BulkBuf[12] = 0x30; /* ASC */ + BulkBuf[13] = 0x01; /* ASCQ */ + BulkBuf[14] = 0x00; + BulkBuf[15] = 0x00; + BulkBuf[16] = 0x00; + BulkBuf[17] = 0x00; + + BulkLen = 18; + DataInTransfer(); +} + + +/* + * MSC SCSI Inquiry Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_Inquiry (void) { + + if (!DataInFormat()) return; + + BulkBuf[ 0] = 0x00; /* Direct Access Device */ + BulkBuf[ 1] = 0x80; /* RMB = 1: Removable Medium */ + BulkBuf[ 2] = 0x00; /* Version: No conformance claim to standard */ + BulkBuf[ 3] = 0x01; + + BulkBuf[ 4] = 36-4; /* Additional Length */ + BulkBuf[ 5] = 0x80; /* SCCS = 1: Storage Controller Component */ + BulkBuf[ 6] = 0x00; + BulkBuf[ 7] = 0x00; + + BulkBuf[ 8] = 'K'; /* Vendor Identification */ + BulkBuf[ 9] = 'e'; + BulkBuf[10] = 'i'; + BulkBuf[11] = 'l'; + BulkBuf[12] = ' '; + BulkBuf[13] = ' '; + BulkBuf[14] = ' '; + BulkBuf[15] = ' '; + + BulkBuf[16] = 'L'; /* Product Identification */ + BulkBuf[17] = 'P'; + BulkBuf[18] = 'C'; + BulkBuf[19] = '1'; + BulkBuf[20] = '3'; + BulkBuf[21] = '4'; + BulkBuf[22] = 'x'; + BulkBuf[23] = ' '; + BulkBuf[24] = 'D'; + BulkBuf[25] = 'i'; + BulkBuf[26] = 's'; + BulkBuf[27] = 'k'; + BulkBuf[28] = ' '; + BulkBuf[29] = ' '; + BulkBuf[30] = ' '; + BulkBuf[31] = ' '; + + BulkBuf[32] = '1'; /* Product Revision Level */ + BulkBuf[33] = '.'; + BulkBuf[34] = '0'; + BulkBuf[35] = ' '; + + BulkLen = 36; + DataInTransfer(); +} + + +/* + * MSC SCSI Mode Sense (6-Byte) Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_ModeSense6 (void) { + + if (!DataInFormat()) return; + + BulkBuf[ 0] = 0x03; + BulkBuf[ 1] = 0x00; + BulkBuf[ 2] = 0x00; + BulkBuf[ 3] = 0x00; + + BulkLen = 4; + DataInTransfer(); +} + + +/* + * MSC SCSI Mode Sense (10-Byte) Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_ModeSense10 (void) { + + if (!DataInFormat()) return; + + BulkBuf[ 0] = 0x00; + BulkBuf[ 1] = 0x06; + BulkBuf[ 2] = 0x00; + BulkBuf[ 3] = 0x00; + BulkBuf[ 4] = 0x00; + BulkBuf[ 5] = 0x00; + BulkBuf[ 6] = 0x00; + BulkBuf[ 7] = 0x00; + + BulkLen = 8; + DataInTransfer(); +} + + +/* + * MSC SCSI Read Capacity Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_ReadCapacity (void) { + + if (!DataInFormat()) return; + + /* Last Logical Block */ + BulkBuf[ 0] = ((MSC_BlockCount - 1) >> 24) & 0xFF; + BulkBuf[ 1] = ((MSC_BlockCount - 1) >> 16) & 0xFF; + BulkBuf[ 2] = ((MSC_BlockCount - 1) >> 8) & 0xFF; + BulkBuf[ 3] = ((MSC_BlockCount - 1) >> 0) & 0xFF; + + /* Block Length */ + BulkBuf[ 4] = (MSC_BlockSize >> 24) & 0xFF; + BulkBuf[ 5] = (MSC_BlockSize >> 16) & 0xFF; + BulkBuf[ 6] = (MSC_BlockSize >> 8) & 0xFF; + BulkBuf[ 7] = (MSC_BlockSize >> 0) & 0xFF; + + BulkLen = 8; + DataInTransfer(); +} + + +/* + * MSC SCSI Read Format Capacity Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_ReadFormatCapacity (void) { + + if (!DataInFormat()) return; + + BulkBuf[ 0] = 0x00; + BulkBuf[ 1] = 0x00; + BulkBuf[ 2] = 0x00; + BulkBuf[ 3] = 0x08; /* Capacity List Length */ + + /* Block Count */ + BulkBuf[ 4] = (MSC_BlockCount >> 24) & 0xFF; + BulkBuf[ 5] = (MSC_BlockCount >> 16) & 0xFF; + BulkBuf[ 6] = (MSC_BlockCount >> 8) & 0xFF; + BulkBuf[ 7] = (MSC_BlockCount >> 0) & 0xFF; + + /* Block Length */ + BulkBuf[ 8] = 0x02; /* Descriptor Code: Formatted Media */ + BulkBuf[ 9] = (MSC_BlockSize >> 16) & 0xFF; + BulkBuf[10] = (MSC_BlockSize >> 8) & 0xFF; + BulkBuf[11] = (MSC_BlockSize >> 0) & 0xFF; + + BulkLen = 12; + DataInTransfer(); +} + + +/* + * MSC Get Command Block Wrapper Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_GetCBW (void) { + uint32_t n; + + for (n = 0; n < BulkLen; n++) { + *((uint8_t *)&CBW + n) = BulkBuf[n]; + } + if ((BulkLen == sizeof(CBW)) && (CBW.dSignature == MSC_CBW_Signature)) { + /* Valid CBW */ + CSW.dTag = CBW.dTag; + CSW.dDataResidue = CBW.dDataLength; + if ((CBW.bLUN != 0) || + (CBW.bCBLength < 1) || + (CBW.bCBLength > 16) ) { +fail: + CSW.bStatus = CSW_CMD_FAILED; + MSC_SetCSW(); + } else { + switch (CBW.CB[0]) { + case SCSI_TEST_UNIT_READY: + MSC_TestUnitReady(); + break; + case SCSI_REQUEST_SENSE: + MSC_RequestSense(); + break; + case SCSI_FORMAT_UNIT: + goto fail; + case SCSI_INQUIRY: + MSC_Inquiry(); + break; + case SCSI_START_STOP_UNIT: + goto fail; + case SCSI_MEDIA_REMOVAL: + goto fail; + case SCSI_MODE_SELECT6: + goto fail; + case SCSI_MODE_SENSE6: + MSC_ModeSense6(); + break; + case SCSI_MODE_SELECT10: + goto fail; + case SCSI_MODE_SENSE10: + MSC_ModeSense10(); + break; + case SCSI_READ_FORMAT_CAPACITIES: + MSC_ReadFormatCapacity(); + break; + case SCSI_READ_CAPACITY: + MSC_ReadCapacity(); + break; + case SCSI_READ10: + case SCSI_READ12: + if (MSC_RWSetup()) { + if ((CBW.bmFlags & 0x80) != 0) { + BulkStage = MSC_BS_DATA_IN; + MSC_MemoryRead(); + } else { /* direction mismatch */ + MSC_SetStallEP(MSC_EP_OUT); + CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(); + } + } + break; + case SCSI_WRITE10: + case SCSI_WRITE12: + if (MSC_RWSetup()) { + if ((CBW.bmFlags & 0x80) == 0) { + BulkStage = MSC_BS_DATA_OUT; + } else { /* direction mismatch */ + MSC_SetStallEP(MSC_EP_IN); + CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(); + } + } + break; + case SCSI_VERIFY10: + if ((CBW.CB[1] & 0x02) == 0) { + // BYTCHK = 0 -> CRC Check (not implemented) + CSW.bStatus = CSW_CMD_PASSED; + MSC_SetCSW(); + break; + } + if (MSC_RWSetup()) { + if ((CBW.bmFlags & 0x80) == 0) { + BulkStage = MSC_BS_DATA_OUT; + MemOK = TRUE; + } else { + MSC_SetStallEP(MSC_EP_IN); + CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(); + } + } + break; + default: + goto fail; + } + } + } else { + /* Invalid CBW */ + MSC_SetStallEP(MSC_EP_IN); + /* set EP to stay stalled */ + USB_EndPointStall |= (MSC_EP_IN & 0x80) ? ((1 << 16) << (MSC_EP_IN & 0x0F)) : (1 << MSC_EP_IN); + MSC_SetStallEP(MSC_EP_OUT); + /* set EP to stay stalled */ + USB_EndPointStall |= (MSC_EP_OUT & 0x80) ? ((1 << 16) << (MSC_EP_OUT & 0x0F)) : (1 << MSC_EP_OUT); + BulkStage = MSC_BS_ERROR; + } +} + + +/* + * MSC Set Command Status Wrapper Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_SetCSW (void) { + + CSW.dSignature = MSC_CSW_Signature; + USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW)); + BulkStage = MSC_BS_CSW; +} + + +/* + * MSC Bulk In Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_BulkIn (void) { + + switch (BulkStage) { + case MSC_BS_DATA_IN: + switch (CBW.CB[0]) { + case SCSI_READ10: + case SCSI_READ12: + MSC_MemoryRead(); + break; + } + break; + case MSC_BS_DATA_IN_LAST: + MSC_SetCSW(); + break; + case MSC_BS_DATA_IN_LAST_STALL: + MSC_SetStallEP(MSC_EP_IN); + MSC_SetCSW(); + break; + case MSC_BS_CSW: + BulkStage = MSC_BS_CBW; + break; + } +} + + +/* + * MSC Bulk Out Callback + * Parameters: None (global variables) + * Return Value: None + */ + +void MSC_BulkOut (void) { + + BulkLen = USB_ReadEP(MSC_EP_OUT, BulkBuf); + switch (BulkStage) { + case MSC_BS_CBW: + MSC_GetCBW(); + break; + case MSC_BS_DATA_OUT: + switch (CBW.CB[0]) { + case SCSI_WRITE10: + case SCSI_WRITE12: + MSC_MemoryWrite(); + break; + case SCSI_VERIFY10: + MSC_MemoryVerify(); + break; + } + break; + default: + MSC_SetStallEP(MSC_EP_OUT); + CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(); + break; + } +} diff --git a/firmware/usbcomp_msd_cdc/src/serial.c b/firmware/usbcomp_msd_cdc/src/serial.c index 390eb92..7b27fd2 100644 --- a/firmware/usbcomp_msd_cdc/src/serial.c +++ b/firmware/usbcomp_msd_cdc/src/serial.c @@ -1,243 +1,243 @@ -/*---------------------------------------------------------------------------- - * Name: serial.c - * Purpose: serial port handling for LPC134x - * Version: V1.10 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ -#include "LPC13xx.h" // LPC13xx definitions -#include "type.h" -#include "serial.h" - - -/*---------------------------------------------------------------------------- - Defines for ring buffers - *---------------------------------------------------------------------------*/ -#define SER_BUF_SIZE (128) // serial buffer in bytes (power 2) -#define SER_BUF_MASK (SER_BUF_SIZE-1ul) // buffer size mask - -/* Buffer read / write macros */ -#define SER_BUF_RESET(serBuf) (serBuf.rdIdx = serBuf.wrIdx = 0) -#define SER_BUF_WR(serBuf, dataIn) (serBuf.data[SER_BUF_MASK & serBuf.wrIdx++] = (dataIn)) -#define SER_BUF_RD(serBuf) (serBuf.data[SER_BUF_MASK & serBuf.rdIdx++]) -#define SER_BUF_EMPTY(serBuf) (serBuf.rdIdx == serBuf.wrIdx) -#define SER_BUF_FULL(serBuf) (serBuf.rdIdx == serBuf.wrIdx+1) -#define SER_BUF_COUNT(serBuf) (SER_BUF_MASK & (serBuf.wrIdx - serBuf.rdIdx)) - -// buffer type -typedef struct __SER_BUF_T { - unsigned char data[SER_BUF_SIZE]; - unsigned int wrIdx; - unsigned int rdIdx; -} SER_BUF_T; - -unsigned long ser_txRestart; // NZ if TX restart is required -unsigned short ser_lineState; // ((msr << 8) | (lsr)) -SER_BUF_T ser_out; // Serial data buffers -SER_BUF_T ser_in; - -/*---------------------------------------------------------------------------- - open the serial port - *---------------------------------------------------------------------------*/ -void ser_OpenPort (void) { - - NVIC_DisableIRQ(UART_IRQn); - - LPC_IOCON->PIO1_6 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO1_6 |= 0x01; /* UART RXD */ - LPC_IOCON->PIO1_7 &= ~0x07; - LPC_IOCON->PIO1_7 |= 0x01; /* UART TXD */ - /* Enable UART clock */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); - LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ - return; -} - -/*---------------------------------------------------------------------------- - close the serial port - *---------------------------------------------------------------------------*/ -void ser_ClosePort (void) { - LPC_IOCON->PIO1_6 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO1_7 &= ~0x07; - - /* Disable the interrupt in the VIC and UART controllers */ - LPC_UART->IER = 0; - NVIC_DisableIRQ(UART_IRQn); - return; -} - -/*---------------------------------------------------------------------------- - initialize the serial port - *---------------------------------------------------------------------------*/ -void ser_InitPort (unsigned long baudrate, unsigned int databits, - unsigned int parity, unsigned int stopbits) { - - uint8_t lcr_p, lcr_s, lcr_d; - uint32_t dll; - uint32_t Fdiv; - - switch (databits) { - case 5: // 5 Data bits - lcr_d = 0x00; - break; - case 6: // 6 Data bits - lcr_d = 0x01; - break; - case 7: // 7 Data bits - lcr_d = 0x02; - break; - case 8: // 8 Data bits - default: - lcr_d = 0x03; - break; - } - - switch (stopbits) { - case 1: // 1,5 Stop bits - case 2: // 2 Stop bits - lcr_s = 0x04; - break; - case 0: // 1 Stop bit - default: - lcr_s = 0x00; - break; - } - - switch (parity) { - case 1: // Parity Odd - lcr_p = 0x08; - break; - case 2: // Parity Even - lcr_p = 0x18; - break; - case 3: // Parity Mark - lcr_p = 0x28; - break; - case 4: // Parity Space - lcr_p = 0x38; - break; - case 0: // Parity None - default: - lcr_p = 0x00; - break; - } - - SER_BUF_RESET(ser_out); // reset out buffer - SER_BUF_RESET(ser_in); // reset in buffer - - /* Note that the pclk is 24,0 MHz. (48.0 MHz / 2) */ - /* 24 MHz PCLK generates also rates for 115200, 57600 baud */ - Fdiv = LPC_SYSCON->UARTCLKDIV; - dll = (((SystemCoreClock/LPC_SYSCON->SYSAHBCLKDIV)/Fdiv)/16)/baudrate ; /*baud rate */ - LPC_UART->FDR = 0; // Fractional divider not used - LPC_UART->LCR = 0x80 | lcr_d | lcr_p | lcr_s; // Data bits, Parity, Stop bit - LPC_UART->DLL = dll; // Baud Rate depending on PCLK - LPC_UART->DLM = (dll >> 8); // High divisor latch - LPC_UART->LCR = 0x00 | lcr_d | lcr_p | lcr_s; // DLAB = 0 - LPC_UART->IER = 0x03; // Enable TX/RX interrupts - - LPC_UART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ - ser_txRestart = 1; // TX fifo is empty - - /* Enable the UART Interrupt */ - NVIC_EnableIRQ(UART_IRQn); - return; -} - -/*---------------------------------------------------------------------------- - read data from serial port - *---------------------------------------------------------------------------*/ -int ser_Read (char *buffer, const int *length) { - int bytesToRead, bytesRead; - - /* Read *length bytes, block if *bytes are not avaialable */ - bytesToRead = *length; - bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length); - bytesRead = bytesToRead; - - while (bytesToRead--) { - while (SER_BUF_EMPTY(ser_in)); // Block until data is available if none - *buffer++ = SER_BUF_RD(ser_in); - } - return (bytesRead); -} - -/*---------------------------------------------------------------------------- - write data to the serial port - *---------------------------------------------------------------------------*/ -int ser_Write (const char *buffer, int *length) { - int bytesToWrite, bytesWritten; - - // Write *length bytes - bytesToWrite = *length; - bytesWritten = bytesToWrite; - - while (!SER_BUF_EMPTY(ser_out)); // Block until space is available if none - while (bytesToWrite) { - SER_BUF_WR(ser_out, *buffer++); // Read Rx FIFO to buffer - bytesToWrite--; - } - - if (ser_txRestart) { - ser_txRestart = 0; - LPC_UART->THR = SER_BUF_RD(ser_out); // Write to the Tx Register - } - - return (bytesWritten); -} - -/*---------------------------------------------------------------------------- - check if character(s) are available at the serial interface - *---------------------------------------------------------------------------*/ -void ser_AvailChar (int *availChar) { - - *availChar = SER_BUF_COUNT(ser_in); - -} - -/*---------------------------------------------------------------------------- - read the line state of the serial port - *---------------------------------------------------------------------------*/ -void ser_LineState (unsigned short *lineState) { - - *lineState = ser_lineState; - ser_lineState = 0; - -} - -/*---------------------------------------------------------------------------- - serial port 1 interrupt - *---------------------------------------------------------------------------*/ -void UART_IRQHandler(void) -{ - volatile unsigned long iir; - - iir = LPC_UART->IIR; - - if ((iir & 0x4) || (iir & 0xC)) { // RDA or CTI pending - while (LPC_UART->LSR & 0x01) { // Rx FIFO is not empty - SER_BUF_WR(ser_in, LPC_UART->RBR); // Read Rx FIFO to buffer - } - } - if ((iir & 0x2)) { // TXMIS pending - if (SER_BUF_COUNT(ser_out) != 0) { - LPC_UART->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO - ser_txRestart = 0; - } - else { - ser_txRestart = 1; - } - } - ser_lineState = LPC_UART->LSR & 0x1E; // update linestate - return; -} - - +/*---------------------------------------------------------------------------- + * Name: serial.c + * Purpose: serial port handling for LPC134x + * Version: V1.10 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#include "LPC13xx.h" // LPC13xx definitions +#include "type.h" +#include "serial.h" + + +/*---------------------------------------------------------------------------- + Defines for ring buffers + *---------------------------------------------------------------------------*/ +#define SER_BUF_SIZE (128) // serial buffer in bytes (power 2) +#define SER_BUF_MASK (SER_BUF_SIZE-1ul) // buffer size mask + +/* Buffer read / write macros */ +#define SER_BUF_RESET(serBuf) (serBuf.rdIdx = serBuf.wrIdx = 0) +#define SER_BUF_WR(serBuf, dataIn) (serBuf.data[SER_BUF_MASK & serBuf.wrIdx++] = (dataIn)) +#define SER_BUF_RD(serBuf) (serBuf.data[SER_BUF_MASK & serBuf.rdIdx++]) +#define SER_BUF_EMPTY(serBuf) (serBuf.rdIdx == serBuf.wrIdx) +#define SER_BUF_FULL(serBuf) (serBuf.rdIdx == serBuf.wrIdx+1) +#define SER_BUF_COUNT(serBuf) (SER_BUF_MASK & (serBuf.wrIdx - serBuf.rdIdx)) + +// buffer type +typedef struct __SER_BUF_T { + unsigned char data[SER_BUF_SIZE]; + unsigned int wrIdx; + unsigned int rdIdx; +} SER_BUF_T; + +unsigned long ser_txRestart; // NZ if TX restart is required +unsigned short ser_lineState; // ((msr << 8) | (lsr)) +SER_BUF_T ser_out; // Serial data buffers +SER_BUF_T ser_in; + +/*---------------------------------------------------------------------------- + open the serial port + *---------------------------------------------------------------------------*/ +void ser_OpenPort (void) { + + NVIC_DisableIRQ(UART_IRQn); + + LPC_IOCON->PIO1_6 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO1_6 |= 0x01; /* UART RXD */ + LPC_IOCON->PIO1_7 &= ~0x07; + LPC_IOCON->PIO1_7 |= 0x01; /* UART TXD */ + /* Enable UART clock */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); + LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ + return; +} + +/*---------------------------------------------------------------------------- + close the serial port + *---------------------------------------------------------------------------*/ +void ser_ClosePort (void) { + LPC_IOCON->PIO1_6 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO1_7 &= ~0x07; + + /* Disable the interrupt in the VIC and UART controllers */ + LPC_UART->IER = 0; + NVIC_DisableIRQ(UART_IRQn); + return; +} + +/*---------------------------------------------------------------------------- + initialize the serial port + *---------------------------------------------------------------------------*/ +void ser_InitPort (unsigned long baudrate, unsigned int databits, + unsigned int parity, unsigned int stopbits) { + + uint8_t lcr_p, lcr_s, lcr_d; + uint32_t dll; + uint32_t Fdiv; + + switch (databits) { + case 5: // 5 Data bits + lcr_d = 0x00; + break; + case 6: // 6 Data bits + lcr_d = 0x01; + break; + case 7: // 7 Data bits + lcr_d = 0x02; + break; + case 8: // 8 Data bits + default: + lcr_d = 0x03; + break; + } + + switch (stopbits) { + case 1: // 1,5 Stop bits + case 2: // 2 Stop bits + lcr_s = 0x04; + break; + case 0: // 1 Stop bit + default: + lcr_s = 0x00; + break; + } + + switch (parity) { + case 1: // Parity Odd + lcr_p = 0x08; + break; + case 2: // Parity Even + lcr_p = 0x18; + break; + case 3: // Parity Mark + lcr_p = 0x28; + break; + case 4: // Parity Space + lcr_p = 0x38; + break; + case 0: // Parity None + default: + lcr_p = 0x00; + break; + } + + SER_BUF_RESET(ser_out); // reset out buffer + SER_BUF_RESET(ser_in); // reset in buffer + + /* Note that the pclk is 24,0 MHz. (48.0 MHz / 2) */ + /* 24 MHz PCLK generates also rates for 115200, 57600 baud */ + Fdiv = LPC_SYSCON->UARTCLKDIV; + dll = (((SystemCoreClock/LPC_SYSCON->SYSAHBCLKDIV)/Fdiv)/16)/baudrate ; /*baud rate */ + LPC_UART->FDR = 0; // Fractional divider not used + LPC_UART->LCR = 0x80 | lcr_d | lcr_p | lcr_s; // Data bits, Parity, Stop bit + LPC_UART->DLL = dll; // Baud Rate depending on PCLK + LPC_UART->DLM = (dll >> 8); // High divisor latch + LPC_UART->LCR = 0x00 | lcr_d | lcr_p | lcr_s; // DLAB = 0 + LPC_UART->IER = 0x03; // Enable TX/RX interrupts + + LPC_UART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ + ser_txRestart = 1; // TX fifo is empty + + /* Enable the UART Interrupt */ + NVIC_EnableIRQ(UART_IRQn); + return; +} + +/*---------------------------------------------------------------------------- + read data from serial port + *---------------------------------------------------------------------------*/ +int ser_Read (char *buffer, const int *length) { + int bytesToRead, bytesRead; + + /* Read *length bytes, block if *bytes are not avaialable */ + bytesToRead = *length; + bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length); + bytesRead = bytesToRead; + + while (bytesToRead--) { + while (SER_BUF_EMPTY(ser_in)); // Block until data is available if none + *buffer++ = SER_BUF_RD(ser_in); + } + return (bytesRead); +} + +/*---------------------------------------------------------------------------- + write data to the serial port + *---------------------------------------------------------------------------*/ +int ser_Write (const char *buffer, int *length) { + int bytesToWrite, bytesWritten; + + // Write *length bytes + bytesToWrite = *length; + bytesWritten = bytesToWrite; + + while (!SER_BUF_EMPTY(ser_out)); // Block until space is available if none + while (bytesToWrite) { + SER_BUF_WR(ser_out, *buffer++); // Read Rx FIFO to buffer + bytesToWrite--; + } + + if (ser_txRestart) { + ser_txRestart = 0; + LPC_UART->THR = SER_BUF_RD(ser_out); // Write to the Tx Register + } + + return (bytesWritten); +} + +/*---------------------------------------------------------------------------- + check if character(s) are available at the serial interface + *---------------------------------------------------------------------------*/ +void ser_AvailChar (int *availChar) { + + *availChar = SER_BUF_COUNT(ser_in); + +} + +/*---------------------------------------------------------------------------- + read the line state of the serial port + *---------------------------------------------------------------------------*/ +void ser_LineState (unsigned short *lineState) { + + *lineState = ser_lineState; + ser_lineState = 0; + +} + +/*---------------------------------------------------------------------------- + serial port 1 interrupt + *---------------------------------------------------------------------------*/ +void UART_IRQHandler(void) +{ + volatile unsigned long iir; + + iir = LPC_UART->IIR; + + if ((iir & 0x4) || (iir & 0xC)) { // RDA or CTI pending + while (LPC_UART->LSR & 0x01) { // Rx FIFO is not empty + SER_BUF_WR(ser_in, LPC_UART->RBR); // Read Rx FIFO to buffer + } + } + if ((iir & 0x2)) { // TXMIS pending + if (SER_BUF_COUNT(ser_out) != 0) { + LPC_UART->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO + ser_txRestart = 0; + } + else { + ser_txRestart = 1; + } + } + ser_lineState = LPC_UART->LSR & 0x1E; // update linestate + return; +} + + diff --git a/firmware/usbcomp_msd_cdc/src/usbcomp.c b/firmware/usbcomp_msd_cdc/src/usbcomp.c index 5b36db8..354472b 100644 --- a/firmware/usbcomp_msd_cdc/src/usbcomp.c +++ b/firmware/usbcomp_msd_cdc/src/usbcomp.c @@ -1,153 +1,153 @@ -/*---------------------------------------------------------------------------- - * Name: vcomdemo.c - * Purpose: USB virtual COM port Demo - * Version: V1.02 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include "LPC13xx.h" -#include "type.h" - -#include "usb.h" -#include "usbcfg.h" -#include "usbhw.h" -#include "usbcore.h" -#include "cdc.h" -#include "cdcuser.h" -#include "serial.h" -#include "vcomdemo.h" -#include "mscuser.h" -#include "memory.h" -#include "stdio.h" -#include "string.h" - - -#include "edubrm.h" - -extern uint8_t Memory[MSC_MemorySize]; /* MSC Memory in RAM */ - -#define EN_TIMER32_1 (1<<10) -#define EN_IOCON (1<<16) -#define EN_USBREG (1<<14) - -/*---------------------------------------------------------------------------- - Initializes the VCOM port. - Call this function before using VCOM_putchar or VCOM_getchar - *---------------------------------------------------------------------------*/ -void VCOM_Init(void) { - - CDC_Init (); -} - - -/*---------------------------------------------------------------------------- - Reads character from serial port buffer and writes to USB buffer - *---------------------------------------------------------------------------*/ -void VCOM_Serial2Usb(void) { - static char serBuf [USB_CDC_BUFSIZE]; - int numBytesRead, numAvailByte; - - ser_AvailChar (&numAvailByte); - if (numAvailByte > 0) { - if (CDC_DepInEmpty) { - numBytesRead = ser_Read (&serBuf[0], &numAvailByte); - - CDC_DepInEmpty = 0; - USB_WriteEP (CDC_DEP_IN, (unsigned char *)&serBuf[0], numBytesRead); - } - } - -} - -/*---------------------------------------------------------------------------- - Reads character from USB buffer and writes to serial port buffer - *---------------------------------------------------------------------------*/ -void VCOM_Usb2Serial(void) { - static char serBuf [32]; - int numBytesToRead, numBytesRead, numAvailByte; - - CDC_OutBufAvailChar (&numAvailByte); - if (numAvailByte > 0) { - numBytesToRead = numAvailByte > 32 ? 32 : numAvailByte; - numBytesRead = CDC_RdOutBuf (&serBuf[0], &numBytesToRead); - ser_Write (&serBuf[0], &numBytesRead); - } - -} - -/*---------------------------------------------------------------------------- - Reads character from USB buffer and writes to serial port buffer - *---------------------------------------------------------------------------*/ -void VCOM_Usb2SerialTest(void) { - static char serBuf [32]; - int numBytesRead; - - strcpy(serBuf,"Test\n"); - numBytesRead = strlen(serBuf); - ser_Write (&serBuf[0], &numBytesRead); - -} - - -/*---------------------------------------------------------------------------- - checks the serial state and initiates notification - *---------------------------------------------------------------------------*/ -void VCOM_CheckSerialState (void) { - unsigned short temp; - static unsigned short serialState; - - temp = CDC_GetSerialState(); - if (serialState != temp) { - serialState = temp; - CDC_NotificationIn(); // send SERIAL_STATE notification - } -} - -/*---------------------------------------------------------------------------- - Main Program - *---------------------------------------------------------------------------*/ -int main (void) { - uint32_t n; - - for (n = 0; n < MSC_ImageSize; n++) { /* Copy Initial Disk Image */ - Memory[n] = DiskImage[n]; /* from Flash to RAM */ - } - - /* Basic chip initialization is taken care of in SystemInit() called - * from the startup code. SystemInit() and chip settings are defined - * in the CMSIS system_.c file. - */ - - /* Enable Timer32_1, IOCON, and USB blocks */ - LPC_SYSCON->SYSAHBCLKCTRL |= (EN_TIMER32_1 | EN_IOCON | EN_USBREG); - - USBIOClkConfig(); - - VCOM_Init(); // VCOM Initialization - - USB_Init(); // USB Initialization - USB_Connect(TRUE); // USB Connect - - while (!USB_Configuration) ; // wait until USB is configured - - //VCOM_Usb2SerialTest(); - - enableLED(); - - while (1) { // Loop forever - VCOM_Brm2Usb(); - VCOM_CheckSerialState(); - VCOM_Usb2Brm(); - } // end while -} // end main () - - +/*---------------------------------------------------------------------------- + * Name: vcomdemo.c + * Purpose: USB virtual COM port Demo + * Version: V1.02 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include "LPC13xx.h" +#include "type.h" + +#include "usb.h" +#include "usbcfg.h" +#include "usbhw.h" +#include "usbcore.h" +#include "cdc.h" +#include "cdcuser.h" +#include "serial.h" +#include "vcomdemo.h" +#include "mscuser.h" +#include "memory.h" +#include "stdio.h" +#include "string.h" + + +#include "edubrm.h" + +extern uint8_t Memory[MSC_MemorySize]; /* MSC Memory in RAM */ + +#define EN_TIMER32_1 (1<<10) +#define EN_IOCON (1<<16) +#define EN_USBREG (1<<14) + +/*---------------------------------------------------------------------------- + Initializes the VCOM port. + Call this function before using VCOM_putchar or VCOM_getchar + *---------------------------------------------------------------------------*/ +void VCOM_Init(void) { + + CDC_Init (); +} + + +/*---------------------------------------------------------------------------- + Reads character from serial port buffer and writes to USB buffer + *---------------------------------------------------------------------------*/ +void VCOM_Serial2Usb(void) { + static char serBuf [USB_CDC_BUFSIZE]; + int numBytesRead, numAvailByte; + + ser_AvailChar (&numAvailByte); + if (numAvailByte > 0) { + if (CDC_DepInEmpty) { + numBytesRead = ser_Read (&serBuf[0], &numAvailByte); + + CDC_DepInEmpty = 0; + USB_WriteEP (CDC_DEP_IN, (unsigned char *)&serBuf[0], numBytesRead); + } + } + +} + +/*---------------------------------------------------------------------------- + Reads character from USB buffer and writes to serial port buffer + *---------------------------------------------------------------------------*/ +void VCOM_Usb2Serial(void) { + static char serBuf [32]; + int numBytesToRead, numBytesRead, numAvailByte; + + CDC_OutBufAvailChar (&numAvailByte); + if (numAvailByte > 0) { + numBytesToRead = numAvailByte > 32 ? 32 : numAvailByte; + numBytesRead = CDC_RdOutBuf (&serBuf[0], &numBytesToRead); + ser_Write (&serBuf[0], &numBytesRead); + } + +} + +/*---------------------------------------------------------------------------- + Reads character from USB buffer and writes to serial port buffer + *---------------------------------------------------------------------------*/ +void VCOM_Usb2SerialTest(void) { + static char serBuf [32]; + int numBytesRead; + + strcpy(serBuf,"Test\n"); + numBytesRead = strlen(serBuf); + ser_Write (&serBuf[0], &numBytesRead); + +} + + +/*---------------------------------------------------------------------------- + checks the serial state and initiates notification + *---------------------------------------------------------------------------*/ +void VCOM_CheckSerialState (void) { + unsigned short temp; + static unsigned short serialState; + + temp = CDC_GetSerialState(); + if (serialState != temp) { + serialState = temp; + CDC_NotificationIn(); // send SERIAL_STATE notification + } +} + +/*---------------------------------------------------------------------------- + Main Program + *---------------------------------------------------------------------------*/ +int main (void) { + uint32_t n; + + for (n = 0; n < MSC_ImageSize; n++) { /* Copy Initial Disk Image */ + Memory[n] = DiskImage[n]; /* from Flash to RAM */ + } + + /* Basic chip initialization is taken care of in SystemInit() called + * from the startup code. SystemInit() and chip settings are defined + * in the CMSIS system_.c file. + */ + + /* Enable Timer32_1, IOCON, and USB blocks */ + LPC_SYSCON->SYSAHBCLKCTRL |= (EN_TIMER32_1 | EN_IOCON | EN_USBREG); + + USBIOClkConfig(); + + VCOM_Init(); // VCOM Initialization + + USB_Init(); // USB Initialization + USB_Connect(TRUE); // USB Connect + + while (!USB_Configuration) ; // wait until USB is configured + + //VCOM_Usb2SerialTest(); + + enableLED(); + + while (1) { // Loop forever + VCOM_Brm2Usb(); + VCOM_CheckSerialState(); + VCOM_Usb2Brm(); + } // end while +} // end main () + + diff --git a/firmware/usbcomp_msd_cdc/src/usbcore.c b/firmware/usbcomp_msd_cdc/src/usbcore.c index 8f6e95b..de97d0f 100644 --- a/firmware/usbcomp_msd_cdc/src/usbcore.c +++ b/firmware/usbcomp_msd_cdc/src/usbcore.c @@ -1,1085 +1,1085 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbcore.c - * Purpose: USB Core Module - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added vendor specific requests - * Changed string descriptor handling - * Reworked Endpoint0 - * V1.00 Initial Version - *----------------------------------------------------------------------------*/ -#include "type.h" - -#include "usb.h" -#include "usbcfg.h" -#include "usbhw.h" -#include "usbcore.h" -#include "usbdesc.h" -#include "usbuser.h" - -#if (USB_CLASS) - -#if (USB_AUDIO) -#include "audio.h" -#include "adcuser.h" -#endif - -#if (USB_HID) -#include "hid.h" -#include "hiduser.h" -#endif - -#if (USB_MSC) -#include "msc.h" -#include "mscuser.h" -extern MSC_CSW CSW; -#endif - -#if (USB_CDC) -#include "cdc.h" -#include "cdcuser.h" -#endif - -#endif - -#if (USB_VENDOR) -#include "vendor.h" -#endif - -uint16_t USB_DeviceStatus; -uint8_t USB_DeviceAddress; -uint8_t USB_Configuration; -uint32_t USB_EndPointMask; -uint32_t USB_EndPointHalt; -uint32_t USB_EndPointStall; /* EP must stay stalled */ -uint8_t USB_NumInterfaces; -uint8_t USB_AltSetting[USB_IF_NUM]; - -uint8_t EP0Buf[USB_MAX_PACKET0]; - - -USB_EP_DATA EP0Data; - -USB_SETUP_PACKET SetupPacket; - - -/* - * Reset USB Core - * Parameters: None - * Return Value: None - */ - -void USB_ResetCore (void) { - - USB_DeviceStatus = USB_POWER; - USB_DeviceAddress = 0; - USB_Configuration = 0; - USB_EndPointMask = 0x00010001; - USB_EndPointHalt = 0x00000000; - USB_EndPointStall = 0x00000000; -} - - -/* - * USB Request - Setup Stage - * Parameters: None (global SetupPacket) - * Return Value: None - */ - -void USB_SetupStage (void) { - USB_ReadEP(0x00, (uint8_t *)&SetupPacket); -} - - -/* - * USB Request - Data In Stage - * Parameters: None (global EP0Data) - * Return Value: None - */ - -void USB_DataInStage (void) { - uint32_t cnt; - - if (EP0Data.Count > USB_MAX_PACKET0) { - cnt = USB_MAX_PACKET0; - } else { - cnt = EP0Data.Count; - } - cnt = USB_WriteEP(0x80, EP0Data.pData, cnt); - EP0Data.pData += cnt; - EP0Data.Count -= cnt; -} - - -/* - * USB Request - Data Out Stage - * Parameters: None (global EP0Data) - * Return Value: None - */ - -void USB_DataOutStage (void) { - uint32_t cnt; - - cnt = USB_ReadEP(0x00, EP0Data.pData); - EP0Data.pData += cnt; - EP0Data.Count -= cnt; -} - - -/* - * USB Request - Status In Stage - * Parameters: None - * Return Value: None - */ - -void USB_StatusInStage (void) { - USB_WriteEP(0x80, NULL, 0); -} - - -/* - * USB Request - Status Out Stage - * Parameters: None - * Return Value: None - */ - -void USB_StatusOutStage (void) { - USB_ReadEP(0x00, EP0Buf); -} - - -/* - * Get Status USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqGetStatus (void) { - uint32_t n, m; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - EP0Data.pData = (uint8_t *)&USB_DeviceStatus; - break; - case REQUEST_TO_INTERFACE: - if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) { - *((uint16_t __attribute__((packed)) *)EP0Buf) = 0; - EP0Data.pData = EP0Buf; - } else { - return (FALSE); - } - break; - case REQUEST_TO_ENDPOINT: - n = SetupPacket.wIndex.WB.L & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - if (((USB_Configuration != 0) || ((n & 0x0F) == 0)) && (USB_EndPointMask & m)) { - *((uint16_t __attribute__((packed)) *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0; - EP0Data.pData = EP0Buf; - } else { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Set/Clear Feature USB Request - * Parameters: sc: 0 - Clear, 1 - Set - * (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqSetClrFeature (uint32_t sc) { - uint32_t n, m; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - if (SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) { - if (sc) { - USB_WakeUpCfg(TRUE); - USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP; - } else { - USB_WakeUpCfg(FALSE); - USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP; - } - } else { - return (FALSE); - } - break; - case REQUEST_TO_INTERFACE: - return (FALSE); - case REQUEST_TO_ENDPOINT: - n = SetupPacket.wIndex.WB.L & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - if ((USB_Configuration != 0) && ((n & 0x0F) != 0) && (USB_EndPointMask & m)) { - if (SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) { - if (sc) { - USB_SetStallEP(n); - USB_EndPointHalt |= m; - } else { - if ((USB_EndPointStall & m) != 0) { - return (TRUE); - } - USB_ClrStallEP(n); -#if (USB_MSC) - if ((n == MSC_EP_IN) && ((USB_EndPointHalt & m) != 0)) { - /* Compliance Test: rewrite CSW after unstall */ - if (CSW.dSignature == MSC_CSW_Signature) { - USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW)); - } - } -#endif - USB_EndPointHalt &= ~m; - } - } else { - return (FALSE); - } - } else { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Set Address USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqSetAddress (void) { - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - USB_DeviceAddress = 0x80 | SetupPacket.wValue.WB.L; - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Get Descriptor USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqGetDescriptor (void) { - uint8_t *pD; - uint32_t len, n; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - switch (SetupPacket.wValue.WB.H) { - case USB_DEVICE_DESCRIPTOR_TYPE: - EP0Data.pData = (uint8_t *)USB_DeviceDescriptor; - len = USB_DEVICE_DESC_SIZE; - break; - case USB_CONFIGURATION_DESCRIPTOR_TYPE: - pD = (uint8_t *)USB_ConfigDescriptor; - for (n = 0; n != SetupPacket.wValue.WB.L; n++) { - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) { - pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; - } - } - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) { - return (FALSE); - } - EP0Data.pData = pD; - len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; - break; - case USB_STRING_DESCRIPTOR_TYPE: - pD = (uint8_t *)USB_StringDescriptor; - for (n = 0; n != SetupPacket.wValue.WB.L; n++) { - if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) { - pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength; - } - } - if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) { - return (FALSE); - } - EP0Data.pData = pD; - len = ((USB_STRING_DESCRIPTOR *)EP0Data.pData)->bLength; - break; - default: - return (FALSE); - } - break; - case REQUEST_TO_INTERFACE: - switch (SetupPacket.wValue.WB.H) { -#if USB_HID - case HID_HID_DESCRIPTOR_TYPE: - if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) { - return (FALSE); /* Only Single HID Interface is supported */ - } - EP0Data.pData = (uint8_t *)USB_ConfigDescriptor + HID_DESC_OFFSET; - len = HID_DESC_SIZE; - break; - case HID_REPORT_DESCRIPTOR_TYPE: - if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) { - return (FALSE); /* Only Single HID Interface is supported */ - } - EP0Data.pData = (uint8_t *)HID_ReportDescriptor; - len = HID_ReportDescSize; - break; - case HID_PHYSICAL_DESCRIPTOR_TYPE: - return (FALSE); /* HID Physical Descriptor is not supported */ -#endif - default: - return (FALSE); - } - break; - default: - return (FALSE); - } - - if (EP0Data.Count > len) { - EP0Data.Count = len; - } - - return (TRUE); -} - - -/* - * Get Configuration USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqGetConfiguration (void) { - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - EP0Data.pData = &USB_Configuration; - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Add a number of bytes to a pointer's address - * Harder than you might think. Some compilers say: - * Expected an lvalue -- Assignment expects its first operand to be - * an lvalue. Please note that a cast removes the lvaluedness of an - * expression. - * - * vpptr = void pointer to pointer - * n = number of bytes to add to pointer - * Call looks like: AddPtr((void **)&myPointer, 8); - */ - -__inline void UsbAddPtr(void **vpptr, uint32_t n) -{ - /* Declare a pointer to a pointer to a byte. Only a byte pointer - * can be incremented by a number of bytes. Other pointers will - * increment by a multiple of what they point to. - */ - uint8_t **bpptr; - - /* Convert our void pointer to a pointer to a byte pointer to a pointer */ - bpptr = (uint8_t **)vpptr; - - /* Add 'n' bytes to our pointer value */ - (*bpptr) += n; -} -/* - * Set Configuration USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqSetConfiguration (void) { - USB_COMMON_DESCRIPTOR *pD; - uint32_t alt = 0; - uint32_t n, m; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - - if (SetupPacket.wValue.WB.L) { - pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor; - while (pD->bLength) { - switch (pD->bDescriptorType) { - case USB_CONFIGURATION_DESCRIPTOR_TYPE: - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == SetupPacket.wValue.WB.L) { - USB_Configuration = SetupPacket.wValue.WB.L; - USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces; - for (n = 0; n < USB_IF_NUM; n++) { - USB_AltSetting[n] = 0; - } - for (n = 1; n < 16; n++) { - if (USB_EndPointMask & (1 << n)) { - USB_DisableEP(n); - } - if (USB_EndPointMask & ((1 << 16) << n)) { - USB_DisableEP(n | 0x80); - } - } - USB_EndPointMask = 0x00010001; - USB_EndPointHalt = 0x00000000; - USB_EndPointStall= 0x00000000; - USB_Configure(TRUE); - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) { - USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED; - } else { - USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED; - } - } else { - UsbAddPtr((void **)&pD, ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength); - continue; - } - break; - case USB_INTERFACE_DESCRIPTOR_TYPE: - alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; - break; - case USB_ENDPOINT_DESCRIPTOR_TYPE: - if (alt == 0) { - n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - USB_EndPointMask |= m; - USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD); - USB_EnableEP(n); - USB_ResetEP(n); - } - break; - } - UsbAddPtr((void **)&pD, pD->bLength); - } - } - else { - USB_Configuration = 0; - for (n = 1; n < 16; n++) { - if (USB_EndPointMask & (1 << n)) { - USB_DisableEP(n); - } - if (USB_EndPointMask & ((1 << 16) << n)) { - USB_DisableEP(n | 0x80); - } - } - USB_EndPointMask = 0x00010001; - USB_EndPointHalt = 0x00000000; - USB_EndPointStall = 0x00000000; - USB_Configure(FALSE); - } - - if (USB_Configuration != SetupPacket.wValue.WB.L) { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Get Interface USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqGetInterface (void) { - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_INTERFACE: - if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) { - EP0Data.pData = USB_AltSetting + SetupPacket.wIndex.WB.L; - } else { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Set Interface USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -__inline uint32_t USB_ReqSetInterface (void) { - USB_COMMON_DESCRIPTOR *pD; - uint32_t ifn = 0, alt = 0, old = 0, msk = 0; - uint32_t n, m; - uint32_t set; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_INTERFACE: - if (USB_Configuration == 0) return (FALSE); - set = FALSE; - pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor; - while (pD->bLength) { - switch (pD->bDescriptorType) { - case USB_CONFIGURATION_DESCRIPTOR_TYPE: - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USB_Configuration) { - UsbAddPtr((void **)&pD, ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength); - continue; - } - break; - case USB_INTERFACE_DESCRIPTOR_TYPE: - ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber; - alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; - msk = 0; - if ((ifn == SetupPacket.wIndex.WB.L) && (alt == SetupPacket.wValue.WB.L)) { - set = TRUE; - old = USB_AltSetting[ifn]; - USB_AltSetting[ifn] = (uint8_t)alt; - } - break; - case USB_ENDPOINT_DESCRIPTOR_TYPE: - if (ifn == SetupPacket.wIndex.WB.L) { - n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - if (alt == SetupPacket.wValue.WB.L) { - USB_EndPointMask |= m; - USB_EndPointHalt &= ~m; - USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD); - USB_EnableEP(n); - USB_ResetEP(n); - msk |= m; - } - else if ((alt == old) && ((msk & m) == 0)) { - USB_EndPointMask &= ~m; - USB_EndPointHalt &= ~m; - USB_DisableEP(n); - } - } - break; - } - UsbAddPtr((void **)&pD, pD->bLength); - } - break; - default: - return (FALSE); - } - - return (set); -} - - -/* - * USB Endpoint 0 Event Callback - * Parameters: event - * Return Value: none - */ - -void USB_EndPoint0 (uint32_t event) { - - switch (event) { - case USB_EVT_SETUP: - USB_SetupStage(); - USB_DirCtrlEP(SetupPacket.bmRequestType.BM.Dir); - EP0Data.Count = SetupPacket.wLength; /* Number of bytes to transfer */ - switch (SetupPacket.bmRequestType.BM.Type) { - - case REQUEST_STANDARD: - switch (SetupPacket.bRequest) { - case USB_REQUEST_GET_STATUS: - if (!USB_ReqGetStatus()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_CLEAR_FEATURE: - if (!USB_ReqSetClrFeature(0)) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_FEATURE_EVENT - USB_Feature_Event(); -#endif - break; - - case USB_REQUEST_SET_FEATURE: - if (!USB_ReqSetClrFeature(1)) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_FEATURE_EVENT - USB_Feature_Event(); -#endif - break; - - case USB_REQUEST_SET_ADDRESS: - if (!USB_ReqSetAddress()) { - goto stall_i; - } - USB_StatusInStage(); - break; - - case USB_REQUEST_GET_DESCRIPTOR: - if (!USB_ReqGetDescriptor()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_SET_DESCRIPTOR: -/*stall_o:*/ USB_SetStallEP(0x00); /* not supported */ - EP0Data.Count = 0; - break; - - case USB_REQUEST_GET_CONFIGURATION: - if (!USB_ReqGetConfiguration()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_SET_CONFIGURATION: - if (!USB_ReqSetConfiguration()) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_CONFIGURE_EVENT - USB_Configure_Event(); -#endif - break; - - case USB_REQUEST_GET_INTERFACE: - if (!USB_ReqGetInterface()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_SET_INTERFACE: - if (!USB_ReqSetInterface()) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_INTERFACE_EVENT - USB_Interface_Event(); -#endif - break; - - default: - goto stall_i; - } - break; /* end case REQUEST_STANDARD */ - -#if USB_CLASS - case REQUEST_CLASS: - switch (SetupPacket.bmRequestType.BM.Recipient) { - - case REQUEST_TO_DEVICE: - goto stall_i; /* not supported */ - - case REQUEST_TO_INTERFACE: -#if USB_HID - if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */ - switch (SetupPacket.bRequest) { - case HID_REQUEST_GET_REPORT: - if (HID_GetReport()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case HID_REQUEST_SET_REPORT: - EP0Data.pData = EP0Buf; /* data to be received */ - goto setup_class_ok; - case HID_REQUEST_GET_IDLE: - if (HID_GetIdle()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case HID_REQUEST_SET_IDLE: - if (HID_SetIdle()) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - case HID_REQUEST_GET_PROTOCOL: - if (HID_GetProtocol()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case HID_REQUEST_SET_PROTOCOL: - if (HID_SetProtocol()) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - } - } -#endif /* USB_HID */ -#if USB_MSC - if (SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) { /* IF number correct? */ - switch (SetupPacket.bRequest) { - case MSC_REQUEST_RESET: - if ((SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */ - (SetupPacket.wLength == 0)) { - if (MSC_Reset()) { - USB_StatusInStage(); - goto setup_class_ok; - } - } - break; - case MSC_REQUEST_GET_MAX_LUN: - if ((SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */ - (SetupPacket.wLength == 1)) { - if (MSC_GetMaxLUN()) { - EP0Data.pData = EP0Buf; - USB_DataInStage(); - goto setup_class_ok; - } - } - break; - } - } -#endif /* USB_MSC */ -#if USB_AUDIO - if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || - (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) { - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_GET_CUR: - case AUDIO_REQUEST_GET_MIN: - case AUDIO_REQUEST_GET_MAX: - case AUDIO_REQUEST_GET_RES: - if (ADC_IF_GetRequest()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - EP0Data.pData = EP0Buf; /* data to be received */ - goto setup_class_ok; - } - } -#endif /* USB_AUDIO */ -#if USB_CDC - if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) { - switch (SetupPacket.bRequest) { - case CDC_SEND_ENCAPSULATED_COMMAND: - EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ - goto setup_class_ok; - case CDC_GET_ENCAPSULATED_RESPONSE: - if (CDC_GetEncapsulatedResponse()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case CDC_SET_COMM_FEATURE: - EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ - goto setup_class_ok; - case CDC_GET_COMM_FEATURE: - if (CDC_GetCommFeature(SetupPacket.wValue.W)) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case CDC_CLEAR_COMM_FEATURE: - if (CDC_ClearCommFeature(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - case CDC_SET_LINE_CODING: - EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ - goto setup_class_ok; - case CDC_GET_LINE_CODING: - if (CDC_GetLineCoding()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case CDC_SET_CONTROL_LINE_STATE: - if (CDC_SetControlLineState(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - case CDC_SEND_BREAK: - if (CDC_SendBreak(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - } - } -#endif /* USB_CDC */ - goto stall_i; /* not supported */ - /* end case REQUEST_TO_INTERFACE */ - - case REQUEST_TO_ENDPOINT: -#if USB_AUDIO - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_GET_CUR: - case AUDIO_REQUEST_GET_MIN: - case AUDIO_REQUEST_GET_MAX: - case AUDIO_REQUEST_GET_RES: - if (ADC_EP_GetRequest()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - EP0Data.pData = EP0Buf; /* data to be received */ - goto setup_class_ok; - } -#endif /* USB_AUDIO */ - goto stall_i; - /* end case REQUEST_TO_ENDPOINT */ - - default: - goto stall_i; - } -setup_class_ok: /* request finished successfully */ - break; /* end case REQUEST_CLASS */ -#endif /* USB_CLASS */ - -#if USB_VENDOR - case REQUEST_VENDOR: - switch (SetupPacket.bmRequestType.BM.Recipient) { - - case REQUEST_TO_DEVICE: - if (!USB_ReqVendorDev(TRUE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_INTERFACE: - if (!USB_ReqVendorIF(TRUE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_ENDPOINT: - if (!USB_ReqVendorEP(TRUE)) { - goto stall_i; /* not supported */ - } - break; - - default: - goto stall_i; - } - - if (SetupPacket.wLength) { - if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) { - USB_DataInStage(); - } - } else { - USB_StatusInStage(); - } - - break; /* end case REQUEST_VENDOR */ -#endif /* USB_VENDOR */ - - default: -stall_i: USB_SetStallEP(0x80); - EP0Data.Count = 0; - break; - } - break; /* end case USB_EVT_SETUP */ - - case USB_EVT_OUT: - if (SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) { - if (EP0Data.Count) { /* still data to receive ? */ - USB_DataOutStage(); /* receive data */ - if (EP0Data.Count == 0) { /* data complete ? */ - switch (SetupPacket.bmRequestType.BM.Type) { - - case REQUEST_STANDARD: - goto stall_i; /* not supported */ - -#if (USB_CLASS) - case REQUEST_CLASS: - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - goto stall_i; /* not supported */ - - case REQUEST_TO_INTERFACE: -#if USB_HID - if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */ - switch (SetupPacket.bRequest) { - case HID_REQUEST_SET_REPORT: - if (HID_SetReport()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } - } -#endif /* USB_HID */ -#if USB_AUDIO - if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || - (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) { - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - if (ADC_IF_SetRequest()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } - } -#endif /* USB_AUDIO */ -#if USB_CDC - if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) { - switch (SetupPacket.bRequest) { - case CDC_SEND_ENCAPSULATED_COMMAND: - if (CDC_SendEncapsulatedCommand()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - case CDC_SET_COMM_FEATURE: - if (CDC_SetCommFeature(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - case CDC_SET_LINE_CODING: - if (CDC_SetLineCoding()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } - } -#endif /* USB_CDC */ - goto stall_i; - /* end case REQUEST_TO_INTERFACE */ - - case REQUEST_TO_ENDPOINT: -#if USB_AUDIO - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - if (ADC_EP_SetRequest()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } -#endif /* USB_AUDIO */ - goto stall_i; - /* end case REQUEST_TO_ENDPOINT */ - - default: - goto stall_i; - } -out_class_ok: /* request finished successfully */ - break; /* end case REQUEST_CLASS */ -#endif /* USB_CLASS */ - -#if USB_VENDOR - case REQUEST_VENDOR: - switch (SetupPacket.bmRequestType.BM.Recipient) { - - case REQUEST_TO_DEVICE: - if (!USB_ReqVendorDev(FALSE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_INTERFACE: - if (!USB_ReqVendorIF(FALSE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_ENDPOINT: - if (!USB_ReqVendorEP(FALSE)) { - goto stall_i; /* not supported */ - } - break; - - default: - goto stall_i; - } - - USB_StatusInStage(); - - break; /* end case REQUEST_VENDOR */ -#endif /* USB_VENDOR */ - - default: - goto stall_i; - } - } - } - } else { - USB_StatusOutStage(); /* receive Acknowledge */ - } - break; /* end case USB_EVT_OUT */ - - case USB_EVT_IN : - if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) { - USB_DataInStage(); /* send data */ - } else { - if (USB_DeviceAddress & 0x80) { - USB_DeviceAddress &= 0x7F; - USB_SetAddress(USB_DeviceAddress); - } - } - break; /* end case USB_EVT_IN */ - - case USB_EVT_OUT_STALL: - USB_ClrStallEP(0x00); - break; - - case USB_EVT_IN_STALL: - USB_ClrStallEP(0x80); - break; - - } -} +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbcore.c + * Purpose: USB Core Module + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------- + * History: + * V1.20 Added vendor specific requests + * Changed string descriptor handling + * Reworked Endpoint0 + * V1.00 Initial Version + *----------------------------------------------------------------------------*/ +#include "type.h" + +#include "usb.h" +#include "usbcfg.h" +#include "usbhw.h" +#include "usbcore.h" +#include "usbdesc.h" +#include "usbuser.h" + +#if (USB_CLASS) + +#if (USB_AUDIO) +#include "audio.h" +#include "adcuser.h" +#endif + +#if (USB_HID) +#include "hid.h" +#include "hiduser.h" +#endif + +#if (USB_MSC) +#include "msc.h" +#include "mscuser.h" +extern MSC_CSW CSW; +#endif + +#if (USB_CDC) +#include "cdc.h" +#include "cdcuser.h" +#endif + +#endif + +#if (USB_VENDOR) +#include "vendor.h" +#endif + +uint16_t USB_DeviceStatus; +uint8_t USB_DeviceAddress; +uint8_t USB_Configuration; +uint32_t USB_EndPointMask; +uint32_t USB_EndPointHalt; +uint32_t USB_EndPointStall; /* EP must stay stalled */ +uint8_t USB_NumInterfaces; +uint8_t USB_AltSetting[USB_IF_NUM]; + +uint8_t EP0Buf[USB_MAX_PACKET0]; + + +USB_EP_DATA EP0Data; + +USB_SETUP_PACKET SetupPacket; + + +/* + * Reset USB Core + * Parameters: None + * Return Value: None + */ + +void USB_ResetCore (void) { + + USB_DeviceStatus = USB_POWER; + USB_DeviceAddress = 0; + USB_Configuration = 0; + USB_EndPointMask = 0x00010001; + USB_EndPointHalt = 0x00000000; + USB_EndPointStall = 0x00000000; +} + + +/* + * USB Request - Setup Stage + * Parameters: None (global SetupPacket) + * Return Value: None + */ + +void USB_SetupStage (void) { + USB_ReadEP(0x00, (uint8_t *)&SetupPacket); +} + + +/* + * USB Request - Data In Stage + * Parameters: None (global EP0Data) + * Return Value: None + */ + +void USB_DataInStage (void) { + uint32_t cnt; + + if (EP0Data.Count > USB_MAX_PACKET0) { + cnt = USB_MAX_PACKET0; + } else { + cnt = EP0Data.Count; + } + cnt = USB_WriteEP(0x80, EP0Data.pData, cnt); + EP0Data.pData += cnt; + EP0Data.Count -= cnt; +} + + +/* + * USB Request - Data Out Stage + * Parameters: None (global EP0Data) + * Return Value: None + */ + +void USB_DataOutStage (void) { + uint32_t cnt; + + cnt = USB_ReadEP(0x00, EP0Data.pData); + EP0Data.pData += cnt; + EP0Data.Count -= cnt; +} + + +/* + * USB Request - Status In Stage + * Parameters: None + * Return Value: None + */ + +void USB_StatusInStage (void) { + USB_WriteEP(0x80, NULL, 0); +} + + +/* + * USB Request - Status Out Stage + * Parameters: None + * Return Value: None + */ + +void USB_StatusOutStage (void) { + USB_ReadEP(0x00, EP0Buf); +} + + +/* + * Get Status USB Request + * Parameters: None (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqGetStatus (void) { + uint32_t n, m; + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_DEVICE: + EP0Data.pData = (uint8_t *)&USB_DeviceStatus; + break; + case REQUEST_TO_INTERFACE: + if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) { + *((uint16_t __attribute__((packed)) *)EP0Buf) = 0; + EP0Data.pData = EP0Buf; + } else { + return (FALSE); + } + break; + case REQUEST_TO_ENDPOINT: + n = SetupPacket.wIndex.WB.L & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + if (((USB_Configuration != 0) || ((n & 0x0F) == 0)) && (USB_EndPointMask & m)) { + *((uint16_t __attribute__((packed)) *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0; + EP0Data.pData = EP0Buf; + } else { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + + +/* + * Set/Clear Feature USB Request + * Parameters: sc: 0 - Clear, 1 - Set + * (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqSetClrFeature (uint32_t sc) { + uint32_t n, m; + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_DEVICE: + if (SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) { + if (sc) { + USB_WakeUpCfg(TRUE); + USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP; + } else { + USB_WakeUpCfg(FALSE); + USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP; + } + } else { + return (FALSE); + } + break; + case REQUEST_TO_INTERFACE: + return (FALSE); + case REQUEST_TO_ENDPOINT: + n = SetupPacket.wIndex.WB.L & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + if ((USB_Configuration != 0) && ((n & 0x0F) != 0) && (USB_EndPointMask & m)) { + if (SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) { + if (sc) { + USB_SetStallEP(n); + USB_EndPointHalt |= m; + } else { + if ((USB_EndPointStall & m) != 0) { + return (TRUE); + } + USB_ClrStallEP(n); +#if (USB_MSC) + if ((n == MSC_EP_IN) && ((USB_EndPointHalt & m) != 0)) { + /* Compliance Test: rewrite CSW after unstall */ + if (CSW.dSignature == MSC_CSW_Signature) { + USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW)); + } + } +#endif + USB_EndPointHalt &= ~m; + } + } else { + return (FALSE); + } + } else { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + + +/* + * Set Address USB Request + * Parameters: None (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqSetAddress (void) { + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_DEVICE: + USB_DeviceAddress = 0x80 | SetupPacket.wValue.WB.L; + break; + default: + return (FALSE); + } + return (TRUE); +} + + +/* + * Get Descriptor USB Request + * Parameters: None (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqGetDescriptor (void) { + uint8_t *pD; + uint32_t len, n; + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_DEVICE: + switch (SetupPacket.wValue.WB.H) { + case USB_DEVICE_DESCRIPTOR_TYPE: + EP0Data.pData = (uint8_t *)USB_DeviceDescriptor; + len = USB_DEVICE_DESC_SIZE; + break; + case USB_CONFIGURATION_DESCRIPTOR_TYPE: + pD = (uint8_t *)USB_ConfigDescriptor; + for (n = 0; n != SetupPacket.wValue.WB.L; n++) { + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) { + pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; + } + } + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) { + return (FALSE); + } + EP0Data.pData = pD; + len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; + break; + case USB_STRING_DESCRIPTOR_TYPE: + pD = (uint8_t *)USB_StringDescriptor; + for (n = 0; n != SetupPacket.wValue.WB.L; n++) { + if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) { + pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength; + } + } + if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) { + return (FALSE); + } + EP0Data.pData = pD; + len = ((USB_STRING_DESCRIPTOR *)EP0Data.pData)->bLength; + break; + default: + return (FALSE); + } + break; + case REQUEST_TO_INTERFACE: + switch (SetupPacket.wValue.WB.H) { +#if USB_HID + case HID_HID_DESCRIPTOR_TYPE: + if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) { + return (FALSE); /* Only Single HID Interface is supported */ + } + EP0Data.pData = (uint8_t *)USB_ConfigDescriptor + HID_DESC_OFFSET; + len = HID_DESC_SIZE; + break; + case HID_REPORT_DESCRIPTOR_TYPE: + if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) { + return (FALSE); /* Only Single HID Interface is supported */ + } + EP0Data.pData = (uint8_t *)HID_ReportDescriptor; + len = HID_ReportDescSize; + break; + case HID_PHYSICAL_DESCRIPTOR_TYPE: + return (FALSE); /* HID Physical Descriptor is not supported */ +#endif + default: + return (FALSE); + } + break; + default: + return (FALSE); + } + + if (EP0Data.Count > len) { + EP0Data.Count = len; + } + + return (TRUE); +} + + +/* + * Get Configuration USB Request + * Parameters: None (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqGetConfiguration (void) { + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_DEVICE: + EP0Data.pData = &USB_Configuration; + break; + default: + return (FALSE); + } + return (TRUE); +} + + +/* + * Add a number of bytes to a pointer's address + * Harder than you might think. Some compilers say: + * Expected an lvalue -- Assignment expects its first operand to be + * an lvalue. Please note that a cast removes the lvaluedness of an + * expression. + * + * vpptr = void pointer to pointer + * n = number of bytes to add to pointer + * Call looks like: AddPtr((void **)&myPointer, 8); + */ + +__inline void UsbAddPtr(void **vpptr, uint32_t n) +{ + /* Declare a pointer to a pointer to a byte. Only a byte pointer + * can be incremented by a number of bytes. Other pointers will + * increment by a multiple of what they point to. + */ + uint8_t **bpptr; + + /* Convert our void pointer to a pointer to a byte pointer to a pointer */ + bpptr = (uint8_t **)vpptr; + + /* Add 'n' bytes to our pointer value */ + (*bpptr) += n; +} +/* + * Set Configuration USB Request + * Parameters: None (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqSetConfiguration (void) { + USB_COMMON_DESCRIPTOR *pD; + uint32_t alt = 0; + uint32_t n, m; + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_DEVICE: + + if (SetupPacket.wValue.WB.L) { + pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor; + while (pD->bLength) { + switch (pD->bDescriptorType) { + case USB_CONFIGURATION_DESCRIPTOR_TYPE: + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == SetupPacket.wValue.WB.L) { + USB_Configuration = SetupPacket.wValue.WB.L; + USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces; + for (n = 0; n < USB_IF_NUM; n++) { + USB_AltSetting[n] = 0; + } + for (n = 1; n < 16; n++) { + if (USB_EndPointMask & (1 << n)) { + USB_DisableEP(n); + } + if (USB_EndPointMask & ((1 << 16) << n)) { + USB_DisableEP(n | 0x80); + } + } + USB_EndPointMask = 0x00010001; + USB_EndPointHalt = 0x00000000; + USB_EndPointStall= 0x00000000; + USB_Configure(TRUE); + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) { + USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED; + } else { + USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED; + } + } else { + UsbAddPtr((void **)&pD, ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength); + continue; + } + break; + case USB_INTERFACE_DESCRIPTOR_TYPE: + alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; + break; + case USB_ENDPOINT_DESCRIPTOR_TYPE: + if (alt == 0) { + n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + USB_EndPointMask |= m; + USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD); + USB_EnableEP(n); + USB_ResetEP(n); + } + break; + } + UsbAddPtr((void **)&pD, pD->bLength); + } + } + else { + USB_Configuration = 0; + for (n = 1; n < 16; n++) { + if (USB_EndPointMask & (1 << n)) { + USB_DisableEP(n); + } + if (USB_EndPointMask & ((1 << 16) << n)) { + USB_DisableEP(n | 0x80); + } + } + USB_EndPointMask = 0x00010001; + USB_EndPointHalt = 0x00000000; + USB_EndPointStall = 0x00000000; + USB_Configure(FALSE); + } + + if (USB_Configuration != SetupPacket.wValue.WB.L) { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + + +/* + * Get Interface USB Request + * Parameters: None (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqGetInterface (void) { + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_INTERFACE: + if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) { + EP0Data.pData = USB_AltSetting + SetupPacket.wIndex.WB.L; + } else { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + + +/* + * Set Interface USB Request + * Parameters: None (global SetupPacket) + * Return Value: TRUE - Success, FALSE - Error + */ + +__inline uint32_t USB_ReqSetInterface (void) { + USB_COMMON_DESCRIPTOR *pD; + uint32_t ifn = 0, alt = 0, old = 0, msk = 0; + uint32_t n, m; + uint32_t set; + + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_INTERFACE: + if (USB_Configuration == 0) return (FALSE); + set = FALSE; + pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor; + while (pD->bLength) { + switch (pD->bDescriptorType) { + case USB_CONFIGURATION_DESCRIPTOR_TYPE: + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USB_Configuration) { + UsbAddPtr((void **)&pD, ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength); + continue; + } + break; + case USB_INTERFACE_DESCRIPTOR_TYPE: + ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber; + alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; + msk = 0; + if ((ifn == SetupPacket.wIndex.WB.L) && (alt == SetupPacket.wValue.WB.L)) { + set = TRUE; + old = USB_AltSetting[ifn]; + USB_AltSetting[ifn] = (uint8_t)alt; + } + break; + case USB_ENDPOINT_DESCRIPTOR_TYPE: + if (ifn == SetupPacket.wIndex.WB.L) { + n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + if (alt == SetupPacket.wValue.WB.L) { + USB_EndPointMask |= m; + USB_EndPointHalt &= ~m; + USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD); + USB_EnableEP(n); + USB_ResetEP(n); + msk |= m; + } + else if ((alt == old) && ((msk & m) == 0)) { + USB_EndPointMask &= ~m; + USB_EndPointHalt &= ~m; + USB_DisableEP(n); + } + } + break; + } + UsbAddPtr((void **)&pD, pD->bLength); + } + break; + default: + return (FALSE); + } + + return (set); +} + + +/* + * USB Endpoint 0 Event Callback + * Parameters: event + * Return Value: none + */ + +void USB_EndPoint0 (uint32_t event) { + + switch (event) { + case USB_EVT_SETUP: + USB_SetupStage(); + USB_DirCtrlEP(SetupPacket.bmRequestType.BM.Dir); + EP0Data.Count = SetupPacket.wLength; /* Number of bytes to transfer */ + switch (SetupPacket.bmRequestType.BM.Type) { + + case REQUEST_STANDARD: + switch (SetupPacket.bRequest) { + case USB_REQUEST_GET_STATUS: + if (!USB_ReqGetStatus()) { + goto stall_i; + } + USB_DataInStage(); + break; + + case USB_REQUEST_CLEAR_FEATURE: + if (!USB_ReqSetClrFeature(0)) { + goto stall_i; + } + USB_StatusInStage(); +#if USB_FEATURE_EVENT + USB_Feature_Event(); +#endif + break; + + case USB_REQUEST_SET_FEATURE: + if (!USB_ReqSetClrFeature(1)) { + goto stall_i; + } + USB_StatusInStage(); +#if USB_FEATURE_EVENT + USB_Feature_Event(); +#endif + break; + + case USB_REQUEST_SET_ADDRESS: + if (!USB_ReqSetAddress()) { + goto stall_i; + } + USB_StatusInStage(); + break; + + case USB_REQUEST_GET_DESCRIPTOR: + if (!USB_ReqGetDescriptor()) { + goto stall_i; + } + USB_DataInStage(); + break; + + case USB_REQUEST_SET_DESCRIPTOR: +/*stall_o:*/ USB_SetStallEP(0x00); /* not supported */ + EP0Data.Count = 0; + break; + + case USB_REQUEST_GET_CONFIGURATION: + if (!USB_ReqGetConfiguration()) { + goto stall_i; + } + USB_DataInStage(); + break; + + case USB_REQUEST_SET_CONFIGURATION: + if (!USB_ReqSetConfiguration()) { + goto stall_i; + } + USB_StatusInStage(); +#if USB_CONFIGURE_EVENT + USB_Configure_Event(); +#endif + break; + + case USB_REQUEST_GET_INTERFACE: + if (!USB_ReqGetInterface()) { + goto stall_i; + } + USB_DataInStage(); + break; + + case USB_REQUEST_SET_INTERFACE: + if (!USB_ReqSetInterface()) { + goto stall_i; + } + USB_StatusInStage(); +#if USB_INTERFACE_EVENT + USB_Interface_Event(); +#endif + break; + + default: + goto stall_i; + } + break; /* end case REQUEST_STANDARD */ + +#if USB_CLASS + case REQUEST_CLASS: + switch (SetupPacket.bmRequestType.BM.Recipient) { + + case REQUEST_TO_DEVICE: + goto stall_i; /* not supported */ + + case REQUEST_TO_INTERFACE: +#if USB_HID + if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */ + switch (SetupPacket.bRequest) { + case HID_REQUEST_GET_REPORT: + if (HID_GetReport()) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case HID_REQUEST_SET_REPORT: + EP0Data.pData = EP0Buf; /* data to be received */ + goto setup_class_ok; + case HID_REQUEST_GET_IDLE: + if (HID_GetIdle()) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case HID_REQUEST_SET_IDLE: + if (HID_SetIdle()) { + USB_StatusInStage(); /* send Acknowledge */ + goto setup_class_ok; + } + break; + case HID_REQUEST_GET_PROTOCOL: + if (HID_GetProtocol()) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case HID_REQUEST_SET_PROTOCOL: + if (HID_SetProtocol()) { + USB_StatusInStage(); /* send Acknowledge */ + goto setup_class_ok; + } + break; + } + } +#endif /* USB_HID */ +#if USB_MSC + if (SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) { /* IF number correct? */ + switch (SetupPacket.bRequest) { + case MSC_REQUEST_RESET: + if ((SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */ + (SetupPacket.wLength == 0)) { + if (MSC_Reset()) { + USB_StatusInStage(); + goto setup_class_ok; + } + } + break; + case MSC_REQUEST_GET_MAX_LUN: + if ((SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */ + (SetupPacket.wLength == 1)) { + if (MSC_GetMaxLUN()) { + EP0Data.pData = EP0Buf; + USB_DataInStage(); + goto setup_class_ok; + } + } + break; + } + } +#endif /* USB_MSC */ +#if USB_AUDIO + if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ + (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || + (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) { + switch (SetupPacket.bRequest) { + case AUDIO_REQUEST_GET_CUR: + case AUDIO_REQUEST_GET_MIN: + case AUDIO_REQUEST_GET_MAX: + case AUDIO_REQUEST_GET_RES: + if (ADC_IF_GetRequest()) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case AUDIO_REQUEST_SET_CUR: +// case AUDIO_REQUEST_SET_MIN: +// case AUDIO_REQUEST_SET_MAX: +// case AUDIO_REQUEST_SET_RES: + EP0Data.pData = EP0Buf; /* data to be received */ + goto setup_class_ok; + } + } +#endif /* USB_AUDIO */ +#if USB_CDC + if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ + (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) { + switch (SetupPacket.bRequest) { + case CDC_SEND_ENCAPSULATED_COMMAND: + EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ + goto setup_class_ok; + case CDC_GET_ENCAPSULATED_RESPONSE: + if (CDC_GetEncapsulatedResponse()) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case CDC_SET_COMM_FEATURE: + EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ + goto setup_class_ok; + case CDC_GET_COMM_FEATURE: + if (CDC_GetCommFeature(SetupPacket.wValue.W)) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case CDC_CLEAR_COMM_FEATURE: + if (CDC_ClearCommFeature(SetupPacket.wValue.W)) { + USB_StatusInStage(); /* send Acknowledge */ + goto setup_class_ok; + } + break; + case CDC_SET_LINE_CODING: + EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ + goto setup_class_ok; + case CDC_GET_LINE_CODING: + if (CDC_GetLineCoding()) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case CDC_SET_CONTROL_LINE_STATE: + if (CDC_SetControlLineState(SetupPacket.wValue.W)) { + USB_StatusInStage(); /* send Acknowledge */ + goto setup_class_ok; + } + break; + case CDC_SEND_BREAK: + if (CDC_SendBreak(SetupPacket.wValue.W)) { + USB_StatusInStage(); /* send Acknowledge */ + goto setup_class_ok; + } + break; + } + } +#endif /* USB_CDC */ + goto stall_i; /* not supported */ + /* end case REQUEST_TO_INTERFACE */ + + case REQUEST_TO_ENDPOINT: +#if USB_AUDIO + switch (SetupPacket.bRequest) { + case AUDIO_REQUEST_GET_CUR: + case AUDIO_REQUEST_GET_MIN: + case AUDIO_REQUEST_GET_MAX: + case AUDIO_REQUEST_GET_RES: + if (ADC_EP_GetRequest()) { + EP0Data.pData = EP0Buf; /* point to data to be sent */ + USB_DataInStage(); /* send requested data */ + goto setup_class_ok; + } + break; + case AUDIO_REQUEST_SET_CUR: +// case AUDIO_REQUEST_SET_MIN: +// case AUDIO_REQUEST_SET_MAX: +// case AUDIO_REQUEST_SET_RES: + EP0Data.pData = EP0Buf; /* data to be received */ + goto setup_class_ok; + } +#endif /* USB_AUDIO */ + goto stall_i; + /* end case REQUEST_TO_ENDPOINT */ + + default: + goto stall_i; + } +setup_class_ok: /* request finished successfully */ + break; /* end case REQUEST_CLASS */ +#endif /* USB_CLASS */ + +#if USB_VENDOR + case REQUEST_VENDOR: + switch (SetupPacket.bmRequestType.BM.Recipient) { + + case REQUEST_TO_DEVICE: + if (!USB_ReqVendorDev(TRUE)) { + goto stall_i; /* not supported */ + } + break; + + case REQUEST_TO_INTERFACE: + if (!USB_ReqVendorIF(TRUE)) { + goto stall_i; /* not supported */ + } + break; + + case REQUEST_TO_ENDPOINT: + if (!USB_ReqVendorEP(TRUE)) { + goto stall_i; /* not supported */ + } + break; + + default: + goto stall_i; + } + + if (SetupPacket.wLength) { + if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) { + USB_DataInStage(); + } + } else { + USB_StatusInStage(); + } + + break; /* end case REQUEST_VENDOR */ +#endif /* USB_VENDOR */ + + default: +stall_i: USB_SetStallEP(0x80); + EP0Data.Count = 0; + break; + } + break; /* end case USB_EVT_SETUP */ + + case USB_EVT_OUT: + if (SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) { + if (EP0Data.Count) { /* still data to receive ? */ + USB_DataOutStage(); /* receive data */ + if (EP0Data.Count == 0) { /* data complete ? */ + switch (SetupPacket.bmRequestType.BM.Type) { + + case REQUEST_STANDARD: + goto stall_i; /* not supported */ + +#if (USB_CLASS) + case REQUEST_CLASS: + switch (SetupPacket.bmRequestType.BM.Recipient) { + case REQUEST_TO_DEVICE: + goto stall_i; /* not supported */ + + case REQUEST_TO_INTERFACE: +#if USB_HID + if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */ + switch (SetupPacket.bRequest) { + case HID_REQUEST_SET_REPORT: + if (HID_SetReport()) { + USB_StatusInStage(); /* send Acknowledge */ + goto out_class_ok; + } + break; + } + } +#endif /* USB_HID */ +#if USB_AUDIO + if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ + (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || + (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) { + switch (SetupPacket.bRequest) { + case AUDIO_REQUEST_SET_CUR: +// case AUDIO_REQUEST_SET_MIN: +// case AUDIO_REQUEST_SET_MAX: +// case AUDIO_REQUEST_SET_RES: + if (ADC_IF_SetRequest()) { + USB_StatusInStage(); /* send Acknowledge */ + goto out_class_ok; + } + break; + } + } +#endif /* USB_AUDIO */ +#if USB_CDC + if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ + (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) { + switch (SetupPacket.bRequest) { + case CDC_SEND_ENCAPSULATED_COMMAND: + if (CDC_SendEncapsulatedCommand()) { + USB_StatusInStage(); /* send Acknowledge */ + goto out_class_ok; + } + break; + case CDC_SET_COMM_FEATURE: + if (CDC_SetCommFeature(SetupPacket.wValue.W)) { + USB_StatusInStage(); /* send Acknowledge */ + goto out_class_ok; + } + break; + case CDC_SET_LINE_CODING: + if (CDC_SetLineCoding()) { + USB_StatusInStage(); /* send Acknowledge */ + goto out_class_ok; + } + break; + } + } +#endif /* USB_CDC */ + goto stall_i; + /* end case REQUEST_TO_INTERFACE */ + + case REQUEST_TO_ENDPOINT: +#if USB_AUDIO + switch (SetupPacket.bRequest) { + case AUDIO_REQUEST_SET_CUR: +// case AUDIO_REQUEST_SET_MIN: +// case AUDIO_REQUEST_SET_MAX: +// case AUDIO_REQUEST_SET_RES: + if (ADC_EP_SetRequest()) { + USB_StatusInStage(); /* send Acknowledge */ + goto out_class_ok; + } + break; + } +#endif /* USB_AUDIO */ + goto stall_i; + /* end case REQUEST_TO_ENDPOINT */ + + default: + goto stall_i; + } +out_class_ok: /* request finished successfully */ + break; /* end case REQUEST_CLASS */ +#endif /* USB_CLASS */ + +#if USB_VENDOR + case REQUEST_VENDOR: + switch (SetupPacket.bmRequestType.BM.Recipient) { + + case REQUEST_TO_DEVICE: + if (!USB_ReqVendorDev(FALSE)) { + goto stall_i; /* not supported */ + } + break; + + case REQUEST_TO_INTERFACE: + if (!USB_ReqVendorIF(FALSE)) { + goto stall_i; /* not supported */ + } + break; + + case REQUEST_TO_ENDPOINT: + if (!USB_ReqVendorEP(FALSE)) { + goto stall_i; /* not supported */ + } + break; + + default: + goto stall_i; + } + + USB_StatusInStage(); + + break; /* end case REQUEST_VENDOR */ +#endif /* USB_VENDOR */ + + default: + goto stall_i; + } + } + } + } else { + USB_StatusOutStage(); /* receive Acknowledge */ + } + break; /* end case USB_EVT_OUT */ + + case USB_EVT_IN : + if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) { + USB_DataInStage(); /* send data */ + } else { + if (USB_DeviceAddress & 0x80) { + USB_DeviceAddress &= 0x7F; + USB_SetAddress(USB_DeviceAddress); + } + } + break; /* end case USB_EVT_IN */ + + case USB_EVT_OUT_STALL: + USB_ClrStallEP(0x00); + break; + + case USB_EVT_IN_STALL: + USB_ClrStallEP(0x80); + break; + + } +} diff --git a/firmware/usbcomp_msd_cdc/src/usbdesc.c b/firmware/usbcomp_msd_cdc/src/usbdesc.c index f41a458..40739b2 100644 --- a/firmware/usbcomp_msd_cdc/src/usbdesc.c +++ b/firmware/usbcomp_msd_cdc/src/usbdesc.c @@ -1,279 +1,279 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbdesc.c - * Purpose: USB Descriptors - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Changed string descriptor handling - * V1.00 Initial Version - *---------------------------------------------------------------------------*/ -#include "type.h" - -#include "usb.h" -#include "cdc.h" -#include "usbcfg.h" -#include "usbdesc.h" - -#include "msc.h" -#include "config.h" - - -/* USB Standard Device Descriptor */ -const uint8_t USB_DeviceDescriptor[] = { - USB_DEVICE_DESC_SIZE, /* bLength */ - USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(0x0200), /* 2.0 */ /* bcdUSB */ - USB_DEVICE_CLASS_MISCELLANEOUS, /* bDeviceClass */ - 0x02, /* bDeviceSubClass */ - 0x01, /* bDeviceProtocol */ - USB_MAX_PACKET0, /* bMaxPacketSize0 */ - -// 0x70, 0x08, /* idVendorL */ //this vendor code is here in order to bypase linux probing for ttyACM0 -// 0x01, 0x00, /* idProductL */ //this product code is here in order to bypase linux probing for ttyACM0 - - WBVAL(USB_VENDOR_ID), /* idVendor */ - WBVAL(USB_PROD_ID), /* idProduct */ - WBVAL(USB_DEVICE), /* 1.00 */ /* bcdDevice */ - 0x01, /* iManufacturer */ - 0x02, /* iProduct */ - 0x03, /* iSerialNumber */ - 0x01 /* bNumConfigurations: one possible configuration*/ -}; - -/* USB Configuration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor) */ -const uint8_t USB_ConfigDescriptor[] = { - /* Configuration 1 */ - USB_CONFIGUARTION_DESC_SIZE, /* bLength */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL( /* wTotalLength */ - 1*USB_CONFIGUARTION_DESC_SIZE + - 1*USB_INTERFACE_DESC_SIZE + /* mass storage interface */ - 2*USB_ENDPOINT_DESC_SIZE + /* bulk endpoints */ - 1*USB_INTERFACE_ASSOCIATION_DESC_SIZE + /* interface association */ - 1*USB_INTERFACE_DESC_SIZE + /* communication interface */ - 0x0013 + /* CDC functions */ - 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */ - 1*USB_INTERFACE_DESC_SIZE + /* data interface */ - 2*USB_ENDPOINT_DESC_SIZE + /* bulk endpoints */ - 0 - ), - - 0x03, /* bNumInterfaces */ - 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */ - 0x00, /* iConfiguration: no string to describe this configuration */ - USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */ - /*USB_CONFIG_REMOTE_WAKEUP*/, - USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */ - - /* Interface 0, Alternate Setting 0, MSC Class */ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_MSC_IF_NUM, /* bInterfaceNumber */ - 0x00, /* bAlternateSetting */ - 0x02, /* bNumEndpoints */ - USB_DEVICE_CLASS_STORAGE, /* bInterfaceClass */ - MSC_SUBCLASS_SCSI, /* bInterfaceSubClass */ - MSC_PROTOCOL_BULK_ONLY, /* bInterfaceProtocol */ - 0x04, /* iInterface */ - - /* Endpoint, EP2 Bulk IN */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(0x0040), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ - - /* Endpoint, EP2 Bulk OUT */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_OUT(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(0x0040), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ - - /* IAD to associate the two CDC interfaces */ - USB_INTERFACE_ASSOCIATION_DESC_SIZE, /* bLength */ - USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_CIF_NUM, /* bFirstInterface */ - 2, /* bInterfaceCount */ - CDC_COMMUNICATION_INTERFACE_CLASS, /* bFunctionClass */ - CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ - 0, /* bFunctionProtocol */ - 0x06, /* iFunction (Index of string descriptor describing this function) */ - - /* Interface 0, Alternate Setting 0, Communication class interface descriptor */ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoint used */ - CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */ - CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x05, /* iInterface: */ - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */ - WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */ - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */ - 0x01, /* bmCapabilities: device handles call management */ - USB_CDC_DIF_NUM, /* bDataInterface: CDC data IF ID */ - /*Abstract Control Management Functional Descriptor*/ - 0x04, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */ - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_UNION, /* bDescriptorSubtype: Union func desc */ - USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */ - USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */ - /*Endpoint 1 Descriptor*/ /* event notification (optional) */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(1), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ - WBVAL(0x0010), /* wMaxPacketSize */ - 0x02, /* 2ms */ /* bInterval */ - /* Interface 1, Alternate Setting 0, Data class interface descriptor*/ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: no alternate setting */ - 0x02, /* bNumEndpoints: two endpoints used */ - CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */ - 0x00, /* bInterfaceSubClass: no subclass available */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x05, /* iInterface: */ - /* Endpoint, EP3 Bulk Out */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_OUT(3), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ - /* Endpoint, EP3 Bulk In */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(3), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ - - /* Terminator */ - 0 /* bLength */ -}; - - -/* USB String Descriptor (optional) */ -const uint8_t USB_StringDescriptor[] = { - /* Index 0x00: LANGID Codes */ - 0x04, /* bLength */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(0x0409), /* US English */ /* wLANGID */ - /* Index 0x01: Manufacturer */ - (13*2 + 2), /* bLength (13 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'N',0, - 'X',0, - 'P',0, - ' ',0, - 'S',0, - 'E',0, - 'M',0, - 'I',0, - 'C',0, - 'O',0, - 'N',0, - 'D',0, - ' ',0, - /* Index 0x02: Product */ - (21*2 + 2), /* bLength ( 21 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'N',0, - 'X',0, - 'P',0, - ' ',0, - 'L',0, - 'P',0, - 'C',0, - '1',0, - '3',0, - 'x',0, - 'x',0, - ' ',0, - 'M',0, - 'S',0, - 'D',0, - '/',0, - 'V',0, - 'C',0, - 'O',0, - 'M',0, - ' ',0, - /* Index 0x03: Serial Number */ - (16*2 + 2), /* bLength (12 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'C',0, - 'O',0, - 'M',0, - 'P',0, - 'O',0, - 'S',0, - 'I',0, - 'T',0, - 'E',0, - ' ',0, - 'D',0, - 'E',0, - 'M',0, - 'O',0, - ' ',0, - ' ',0, - /* Index 0x04: Interface 0, Alternate Setting 0 */ - ( 6*2 + 2), /* bLength (6 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'M',0, - 'e',0, - 'm',0, - 'o',0, - 'r',0, - 'y',0, - /* Index 0x05: Interface 0, Alternate Setting 0 */ - ( 4*2 + 2), /* bLength (4 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'V',0, - 'C',0, - 'O',0, - 'M',0, - /* Index 0x05: Interface 0, Alternate Setting 0 */ - ( 8*2 + 2), /* bLength (4 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'C',0, - 'O',0, - 'M',0, - '/',0, - 'D',0, - 'A',0, - 'T',0, - 'A',0, -}; +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbdesc.c + * Purpose: USB Descriptors + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------- + * History: + * V1.20 Changed string descriptor handling + * V1.00 Initial Version + *---------------------------------------------------------------------------*/ +#include "type.h" + +#include "usb.h" +#include "cdc.h" +#include "usbcfg.h" +#include "usbdesc.h" + +#include "msc.h" +#include "config.h" + + +/* USB Standard Device Descriptor */ +const uint8_t USB_DeviceDescriptor[] = { + USB_DEVICE_DESC_SIZE, /* bLength */ + USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */ + WBVAL(0x0200), /* 2.0 */ /* bcdUSB */ + USB_DEVICE_CLASS_MISCELLANEOUS, /* bDeviceClass */ + 0x02, /* bDeviceSubClass */ + 0x01, /* bDeviceProtocol */ + USB_MAX_PACKET0, /* bMaxPacketSize0 */ + +// 0x70, 0x08, /* idVendorL */ //this vendor code is here in order to bypase linux probing for ttyACM0 +// 0x01, 0x00, /* idProductL */ //this product code is here in order to bypase linux probing for ttyACM0 + + WBVAL(USB_VENDOR_ID), /* idVendor */ + WBVAL(USB_PROD_ID), /* idProduct */ + WBVAL(USB_DEVICE), /* 1.00 */ /* bcdDevice */ + 0x01, /* iManufacturer */ + 0x02, /* iProduct */ + 0x03, /* iSerialNumber */ + 0x01 /* bNumConfigurations: one possible configuration*/ +}; + +/* USB Configuration Descriptor */ +/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor) */ +const uint8_t USB_ConfigDescriptor[] = { + /* Configuration 1 */ + USB_CONFIGUARTION_DESC_SIZE, /* bLength */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ + WBVAL( /* wTotalLength */ + 1*USB_CONFIGUARTION_DESC_SIZE + + 1*USB_INTERFACE_DESC_SIZE + /* mass storage interface */ + 2*USB_ENDPOINT_DESC_SIZE + /* bulk endpoints */ + 1*USB_INTERFACE_ASSOCIATION_DESC_SIZE + /* interface association */ + 1*USB_INTERFACE_DESC_SIZE + /* communication interface */ + 0x0013 + /* CDC functions */ + 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */ + 1*USB_INTERFACE_DESC_SIZE + /* data interface */ + 2*USB_ENDPOINT_DESC_SIZE + /* bulk endpoints */ + 0 + ), + + 0x03, /* bNumInterfaces */ + 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */ + 0x00, /* iConfiguration: no string to describe this configuration */ + USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */ + /*USB_CONFIG_REMOTE_WAKEUP*/, + USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */ + + /* Interface 0, Alternate Setting 0, MSC Class */ + USB_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_MSC_IF_NUM, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x02, /* bNumEndpoints */ + USB_DEVICE_CLASS_STORAGE, /* bInterfaceClass */ + MSC_SUBCLASS_SCSI, /* bInterfaceSubClass */ + MSC_PROTOCOL_BULK_ONLY, /* bInterfaceProtocol */ + 0x04, /* iInterface */ + + /* Endpoint, EP2 Bulk IN */ + USB_ENDPOINT_DESC_SIZE, /* bLength */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_ENDPOINT_IN(2), /* bEndpointAddress */ + USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ + WBVAL(0x0040), /* wMaxPacketSize */ + 0x00, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint, EP2 Bulk OUT */ + USB_ENDPOINT_DESC_SIZE, /* bLength */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_ENDPOINT_OUT(2), /* bEndpointAddress */ + USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ + WBVAL(0x0040), /* wMaxPacketSize */ + 0x00, /* bInterval: ignore for Bulk transfer */ + + /* IAD to associate the two CDC interfaces */ + USB_INTERFACE_ASSOCIATION_DESC_SIZE, /* bLength */ + USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_CDC_CIF_NUM, /* bFirstInterface */ + 2, /* bInterfaceCount */ + CDC_COMMUNICATION_INTERFACE_CLASS, /* bFunctionClass */ + CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ + 0, /* bFunctionProtocol */ + 0x06, /* iFunction (Index of string descriptor describing this function) */ + + /* Interface 0, Alternate Setting 0, Communication class interface descriptor */ + USB_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */ + CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */ + 0x00, /* bInterfaceProtocol: no protocol used */ + 0x05, /* iInterface: */ + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ + CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */ + WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */ + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ + CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */ + 0x01, /* bmCapabilities: device handles call management */ + USB_CDC_DIF_NUM, /* bDataInterface: CDC data IF ID */ + /*Abstract Control Management Functional Descriptor*/ + 0x04, /* bFunctionLength */ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ + CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */ + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ + CDC_UNION, /* bDescriptorSubtype: Union func desc */ + USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */ + USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */ + /*Endpoint 1 Descriptor*/ /* event notification (optional) */ + USB_ENDPOINT_DESC_SIZE, /* bLength */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_ENDPOINT_IN(1), /* bEndpointAddress */ + USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ + WBVAL(0x0010), /* wMaxPacketSize */ + 0x02, /* 2ms */ /* bInterval */ + /* Interface 1, Alternate Setting 0, Data class interface descriptor*/ + USB_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: no alternate setting */ + 0x02, /* bNumEndpoints: two endpoints used */ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */ + 0x00, /* bInterfaceSubClass: no subclass available */ + 0x00, /* bInterfaceProtocol: no protocol used */ + 0x05, /* iInterface: */ + /* Endpoint, EP3 Bulk Out */ + USB_ENDPOINT_DESC_SIZE, /* bLength */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_ENDPOINT_OUT(3), /* bEndpointAddress */ + USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ + WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ + 0x00, /* bInterval: ignore for Bulk transfer */ + /* Endpoint, EP3 Bulk In */ + USB_ENDPOINT_DESC_SIZE, /* bLength */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + USB_ENDPOINT_IN(3), /* bEndpointAddress */ + USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ + WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ + 0x00, /* bInterval: ignore for Bulk transfer */ + + /* Terminator */ + 0 /* bLength */ +}; + + +/* USB String Descriptor (optional) */ +const uint8_t USB_StringDescriptor[] = { + /* Index 0x00: LANGID Codes */ + 0x04, /* bLength */ + USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ + WBVAL(0x0409), /* US English */ /* wLANGID */ + /* Index 0x01: Manufacturer */ + (13*2 + 2), /* bLength (13 Char + Type + lenght) */ + USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ + 'N',0, + 'X',0, + 'P',0, + ' ',0, + 'S',0, + 'E',0, + 'M',0, + 'I',0, + 'C',0, + 'O',0, + 'N',0, + 'D',0, + ' ',0, + /* Index 0x02: Product */ + (21*2 + 2), /* bLength ( 21 Char + Type + lenght) */ + USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ + 'N',0, + 'X',0, + 'P',0, + ' ',0, + 'L',0, + 'P',0, + 'C',0, + '1',0, + '3',0, + 'x',0, + 'x',0, + ' ',0, + 'M',0, + 'S',0, + 'D',0, + '/',0, + 'V',0, + 'C',0, + 'O',0, + 'M',0, + ' ',0, + /* Index 0x03: Serial Number */ + (16*2 + 2), /* bLength (12 Char + Type + lenght) */ + USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ + 'C',0, + 'O',0, + 'M',0, + 'P',0, + 'O',0, + 'S',0, + 'I',0, + 'T',0, + 'E',0, + ' ',0, + 'D',0, + 'E',0, + 'M',0, + 'O',0, + ' ',0, + ' ',0, + /* Index 0x04: Interface 0, Alternate Setting 0 */ + ( 6*2 + 2), /* bLength (6 Char + Type + lenght) */ + USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ + 'M',0, + 'e',0, + 'm',0, + 'o',0, + 'r',0, + 'y',0, + /* Index 0x05: Interface 0, Alternate Setting 0 */ + ( 4*2 + 2), /* bLength (4 Char + Type + lenght) */ + USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ + 'V',0, + 'C',0, + 'O',0, + 'M',0, + /* Index 0x05: Interface 0, Alternate Setting 0 */ + ( 8*2 + 2), /* bLength (4 Char + Type + lenght) */ + USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ + 'C',0, + 'O',0, + 'M',0, + '/',0, + 'D',0, + 'A',0, + 'T',0, + 'A',0, +}; diff --git a/firmware/usbcomp_msd_cdc/src/usbhw.c b/firmware/usbcomp_msd_cdc/src/usbhw.c index 12e7b9c..2874b7a 100644 --- a/firmware/usbcomp_msd_cdc/src/usbhw.c +++ b/firmware/usbcomp_msd_cdc/src/usbhw.c @@ -1,552 +1,552 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbhw.c - * Purpose: USB Hardware Layer Module for Philips LPC17xx - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added USB_ClearEPBuf - * V1.00 Initial Version - *----------------------------------------------------------------------------*/ -#include "LPC13xx.h" /* LPC13xx definitions */ -#include "usb.h" -#include "usbcfg.h" -#include "usbreg.h" -#include "usbhw.h" -#include "usbcore.h" -#include "usbuser.h" - - -/* - * USB and IO Clock configuration only. - * The same as call PeriClkIOInit(IOCON_USB); - * The purpose is to reduce the code space for - * overall USB project and reserve code space for - * USB debugging. - * Parameters: None - * Return Value: None - */ -void USBIOClkConfig( void ) -{ - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - LPC_IOCON->PIO0_1 &= ~0x07; - LPC_IOCON->PIO0_1 |= 0x01; /* CLK OUT */ - - /* Enable AHB clock to the USB block. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<14); - LPC_IOCON->PIO0_3 &= ~0x1F; - LPC_IOCON->PIO0_3 |= 0x01; /* Secondary function VBUS */ - LPC_IOCON->PIO0_6 &= ~0x07; - LPC_IOCON->PIO0_6 |= 0x01; /* Secondary function SoftConn */ - return; -} - -/* - * Delay number of clock cycles - * Parameters: Delay length - * Return Value: None - */ - -void delay (uint32_t length ) { - uint32_t i; - - for ( i = 0; i < length; i++ ); - return; -} - -/* - * Get Endpoint Physical Address - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: Endpoint Physical Address - */ - -uint32_t EPAdr (uint32_t EPNum) { - uint32_t val; - - val = (EPNum & 0x0F) << 1; - if (EPNum & 0x80) { - val += 1; - } - return (val); -} - - -/* - * Write Command - * Parameters: cmd: Command - * Return Value: None - */ - -void WrCmd (uint32_t cmd) { - - LPC_USB->DevIntClr = CCEMTY_INT; - LPC_USB->CmdCode = cmd; - while ((LPC_USB->DevIntSt & (CCEMTY_INT | DEV_STAT_INT)) == 0); -} - - -/* - * Write Command Data - * Parameters: cmd: Command - * val: Data - * Return Value: None - */ - -void WrCmdDat (uint32_t cmd, uint32_t val) { - - WrCmd(cmd); - WrCmd(val); -} - - -/* - * Write Command to Endpoint - * Parameters: cmd: Command - * val: Data - * Return Value: None - */ - -void WrCmdEP (uint32_t EPNum, uint32_t cmd){ - - WrCmd(CMD_SEL_EP(EPAdr(EPNum))); - WrCmd(cmd); -} - - -/* - * Read Command Data - * Parameters: cmd: Command - * Return Value: Data Value - */ - -uint32_t RdCmdDat (uint32_t cmd) { - - LPC_USB->DevIntClr = CCEMTY_INT | CDFULL_INT; - LPC_USB->CmdCode = cmd; - while ((LPC_USB->DevIntSt & (CDFULL_INT | DEV_STAT_INT)) == 0); - return (LPC_USB->CmdData); -} - - -/* - * USB Initialize Function - * Called by the User to initialize USB - * Return Value: None - */ - -void USB_Init (void) { - -#if USB_FIQ_EVENT - /* It's important that only BULK and FRAME(ISO) can be routed - to FIQ. */ - LPC_USB->DevFIQSel = 0x01; /* SOF Use FIQ */ - - /* Enable the USB Interrupt */ - NVIC_EnableIRQ(USB_FIQn); -#endif - - /* Enable the USB Interrupt */ - NVIC_EnableIRQ(USB_IRQn); - - USB_Reset(); - USB_SetAddress(0); - return; -} - - -/* - * USB Connect Function - * Called by the User to Connect/Disconnect USB - * Parameters: con: Connect/Disconnect - * Return Value: None - */ - -void USB_Connect (uint32_t con) { - WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(con ? DEV_CON : 0)); -} - - -/* - * USB Reset Function - * Called automatically on USB Reset - * Return Value: None - */ - -void USB_Reset (void) { - - LPC_USB->DevIntClr = 0x000FFFFF; - /* Enable all eight(8) EPs, note: EP won't be ready until it's - configured/enabled when device sending SetEPStatus command - to the command engine. */ - LPC_USB->DevIntEn = DEV_STAT_INT | (0xFF<<1) | - (USB_SOF_EVENT ? FRAME_INT : 0); - return; -} - - -/* - * USB Suspend Function - * Called automatically on USB Suspend - * Return Value: None - */ - -void USB_Suspend (void) { - /* Performed by Hardware */ -} - - -/* - * USB Resume Function - * Called automatically on USB Resume - * Return Value: None - */ - -void USB_Resume (void) { - /* Performed by Hardware */ -} - - -/* - * USB Remote Wakeup Function - * Called automatically on USB Remote Wakeup - * Return Value: None - */ - -void USB_WakeUp (void) { - - if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP) { - WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); - } -} - - -/* - * USB Remote Wakeup Configuration Function - * Parameters: cfg: Enable/Disable - * Return Value: None - */ - -void USB_WakeUpCfg (uint32_t cfg) { - cfg = cfg; /* Not needed */ -} - - -/* - * USB Set Address Function - * Parameters: adr: USB Address - * Return Value: None - */ - -void USB_SetAddress (uint32_t adr) { - WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Don't wait for next */ - WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Setup Status Phase */ -} - - -/* - * USB Configure Function - * Parameters: cfg: Configure/Deconfigure - * Return Value: None - */ - -void USB_Configure (uint32_t cfg) { - - WrCmdDat(CMD_CFG_DEV, DAT_WR_BYTE(cfg ? CONF_DVICE : 0)); - return; -} - - -/* - * Configure USB Endpoint according to Descriptor - * Parameters: pEPD: Pointer to Endpoint Descriptor - * Return Value: None - */ - -void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) { - return; -} - - -/* - * Set Direction for USB Control Endpoint - * Parameters: dir: Out (dir == 0), In (dir <> 0) - * Return Value: None - */ - -void USB_DirCtrlEP (uint32_t dir) { - dir = dir; /* Not needed */ -} - - -/* - * Enable USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_EnableEP (uint32_t EPNum) { - WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0)); -} - - -/* - * Disable USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_DisableEP (uint32_t EPNum) { - WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_DA)); -} - - -/* - * Reset USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_ResetEP (uint32_t EPNum) { - WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0)); -} - - -/* - * Set Stall for USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_SetStallEP (uint32_t EPNum) { - WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_ST)); -} - - -/* - * Clear Stall for USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_ClrStallEP (uint32_t EPNum) { - WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0)); -} - - -/* - * Clear USB Endpoint Buffer - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_ClearEPBuf (uint32_t EPNum) { - WrCmdEP(EPNum, CMD_CLR_BUF); -} - - -/* - * Read USB Endpoint Data - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * pData: Pointer to Data Buffer - * Return Value: Number of bytes read - */ - -uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData) { - uint32_t cnt, n; - - LPC_USB->Ctrl = ((EPNum & 0x0F) << 2) | CTRL_RD_EN; - /* 3 clock cycles to fetch the packet length from RAM. */ - delay( 5 ); - - do { - cnt = LPC_USB->RxPLen; - } while ((cnt & PKT_DV) == 0); - cnt &= PKT_LNGTH_MASK; - - for (n = 0; n < (cnt + 3) / 4; n++) { - *((uint32_t __attribute__((packed)) *)pData) = LPC_USB->RxData; - pData += 4; - } - - LPC_USB->Ctrl = 0; - - if ((EPNum & 0x80) != 0x04) { /* Non-Isochronous Endpoint */ - WrCmdEP(EPNum, CMD_CLR_BUF); - } - - return (cnt); -} - - -/* - * Write USB Endpoint Data - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * pData: Pointer to Data Buffer - * cnt: Number of bytes to write - * Return Value: Number of bytes written - */ - -uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) { - uint32_t n; - - LPC_USB->Ctrl = ((EPNum & 0x0F) << 2) | CTRL_WR_EN; - /* 3 clock cycles to fetch the packet length from RAM. */ - delay( 5 ); - LPC_USB->TxPLen = cnt; - - for (n = 0; n < (cnt + 3) / 4; n++) { - LPC_USB->TxData = *((uint32_t __attribute__((packed)) *)pData); - pData += 4; - } - - LPC_USB->Ctrl = 0; - - WrCmdEP(EPNum, CMD_VALID_BUF); - - return (cnt); -} - -/* - * Get USB Last Frame Number - * Parameters: None - * Return Value: Frame Number - */ - -uint32_t USB_GetFrame (void) { - uint32_t val; - - WrCmd(CMD_RD_FRAME); - val = RdCmdDat(DAT_RD_FRAME); - val = val | (RdCmdDat(DAT_RD_FRAME) << 8); - - return (val); -} - - -/* - * USB Interrupt Service Routine - */ - -void USB_IRQHandler (void) -{ - uint32_t disr, val, n, m; - - disr = LPC_USB->DevIntSt; /* Device Interrupt Status */ - LPC_USB->DevIntClr = disr; - - /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */ - if (disr & DEV_STAT_INT) { - WrCmd(CMD_GET_DEV_STAT); - val = RdCmdDat(DAT_GET_DEV_STAT); /* Device Status */ - if (val & DEV_RST) { /* Reset */ - USB_Reset(); -#if USB_RESET_EVENT - USB_Reset_Event(); -#endif - } - if (val & DEV_CON_CH) { /* Connect change */ -#if USB_POWER_EVENT - USB_Power_Event(val & DEV_CON); -#endif - } - if (val & DEV_SUS_CH) { /* Suspend/Resume */ - if (val & DEV_SUS) { /* Suspend */ - USB_Suspend(); -#if USB_SUSPEND_EVENT - USB_Suspend_Event(); -#endif - } else { /* Resume */ - USB_Resume(); -#if USB_RESUME_EVENT - USB_Resume_Event(); -#endif - } - } - goto isr_end; - } - -#if USB_SOF_EVENT - /* Start of Frame Interrupt */ - if (disr & FRAME_INT) { - LPC_USB->DevIntClr = FRAME_INT; - USB_SOF_Event(); - SOFIRQCount++; - } -#endif - -#if USB_ERROR_EVENT - /* NO error interrupt anymore, below code can be used - as example to get error status from command engine. */ - /* Error Interrupt */ - if (disr & ERR_INT) { - WrCmd(CMD_RD_ERR_STAT); - val = RdCmdDat(DAT_RD_ERR_STAT); - USB_Error_Event(val); - } -#endif - - /* Endpoint's Interrupt */ - if (disr & (0xFF<<1)) { - /* if any of the EP0 through EP7 is set, or bit 1 through 9 on disr */ - for (n = 0; n < USB_EP_NUM; n++) { /* Check All Endpoints */ - /* skip frame interrupt at bit 0 in disr */ -// if (disr & ((1 << n)<<1)) { - if ((disr>>1) & (1 << n)) { - m = n >> 1; - /* clear EP interrupt by sending cmd to the command engine. */ - WrCmd(CMD_SEL_EP_CLRI(n)); - val = RdCmdDat(DAT_SEL_EP_CLRI(n)); - if ((n & 1) == 0) { /* OUT Endpoint */ - if (n == 0) { /* Control OUT Endpoint */ - if (val & EP_SEL_STP) { /* Setup Packet */ - if (USB_P_EP[0]) { - USB_P_EP[0](USB_EVT_SETUP); - continue; - } - } - } - if (USB_P_EP[m]) { - USB_P_EP[m](USB_EVT_OUT); - } - } else { /* IN Endpoint */ - if (USB_P_EP[m]) { - USB_P_EP[m](USB_EVT_IN); - } - } - } - } - } -isr_end: - return; -} +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbhw.c + * Purpose: USB Hardware Layer Module for Philips LPC17xx + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------- + * History: + * V1.20 Added USB_ClearEPBuf + * V1.00 Initial Version + *----------------------------------------------------------------------------*/ +#include "LPC13xx.h" /* LPC13xx definitions */ +#include "usb.h" +#include "usbcfg.h" +#include "usbreg.h" +#include "usbhw.h" +#include "usbcore.h" +#include "usbuser.h" + + +/* + * USB and IO Clock configuration only. + * The same as call PeriClkIOInit(IOCON_USB); + * The purpose is to reduce the code space for + * overall USB project and reserve code space for + * USB debugging. + * Parameters: None + * Return Value: None + */ +void USBIOClkConfig( void ) +{ + /* Enable AHB clock to the GPIO domain. */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); + + LPC_IOCON->PIO0_1 &= ~0x07; + LPC_IOCON->PIO0_1 |= 0x01; /* CLK OUT */ + + /* Enable AHB clock to the USB block. */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<14); + LPC_IOCON->PIO0_3 &= ~0x1F; + LPC_IOCON->PIO0_3 |= 0x01; /* Secondary function VBUS */ + LPC_IOCON->PIO0_6 &= ~0x07; + LPC_IOCON->PIO0_6 |= 0x01; /* Secondary function SoftConn */ + return; +} + +/* + * Delay number of clock cycles + * Parameters: Delay length + * Return Value: None + */ + +void delay (uint32_t length ) { + uint32_t i; + + for ( i = 0; i < length; i++ ); + return; +} + +/* + * Get Endpoint Physical Address + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: Endpoint Physical Address + */ + +uint32_t EPAdr (uint32_t EPNum) { + uint32_t val; + + val = (EPNum & 0x0F) << 1; + if (EPNum & 0x80) { + val += 1; + } + return (val); +} + + +/* + * Write Command + * Parameters: cmd: Command + * Return Value: None + */ + +void WrCmd (uint32_t cmd) { + + LPC_USB->DevIntClr = CCEMTY_INT; + LPC_USB->CmdCode = cmd; + while ((LPC_USB->DevIntSt & (CCEMTY_INT | DEV_STAT_INT)) == 0); +} + + +/* + * Write Command Data + * Parameters: cmd: Command + * val: Data + * Return Value: None + */ + +void WrCmdDat (uint32_t cmd, uint32_t val) { + + WrCmd(cmd); + WrCmd(val); +} + + +/* + * Write Command to Endpoint + * Parameters: cmd: Command + * val: Data + * Return Value: None + */ + +void WrCmdEP (uint32_t EPNum, uint32_t cmd){ + + WrCmd(CMD_SEL_EP(EPAdr(EPNum))); + WrCmd(cmd); +} + + +/* + * Read Command Data + * Parameters: cmd: Command + * Return Value: Data Value + */ + +uint32_t RdCmdDat (uint32_t cmd) { + + LPC_USB->DevIntClr = CCEMTY_INT | CDFULL_INT; + LPC_USB->CmdCode = cmd; + while ((LPC_USB->DevIntSt & (CDFULL_INT | DEV_STAT_INT)) == 0); + return (LPC_USB->CmdData); +} + + +/* + * USB Initialize Function + * Called by the User to initialize USB + * Return Value: None + */ + +void USB_Init (void) { + +#if USB_FIQ_EVENT + /* It's important that only BULK and FRAME(ISO) can be routed + to FIQ. */ + LPC_USB->DevFIQSel = 0x01; /* SOF Use FIQ */ + + /* Enable the USB Interrupt */ + NVIC_EnableIRQ(USB_FIQn); +#endif + + /* Enable the USB Interrupt */ + NVIC_EnableIRQ(USB_IRQn); + + USB_Reset(); + USB_SetAddress(0); + return; +} + + +/* + * USB Connect Function + * Called by the User to Connect/Disconnect USB + * Parameters: con: Connect/Disconnect + * Return Value: None + */ + +void USB_Connect (uint32_t con) { + WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(con ? DEV_CON : 0)); +} + + +/* + * USB Reset Function + * Called automatically on USB Reset + * Return Value: None + */ + +void USB_Reset (void) { + + LPC_USB->DevIntClr = 0x000FFFFF; + /* Enable all eight(8) EPs, note: EP won't be ready until it's + configured/enabled when device sending SetEPStatus command + to the command engine. */ + LPC_USB->DevIntEn = DEV_STAT_INT | (0xFF<<1) | + (USB_SOF_EVENT ? FRAME_INT : 0); + return; +} + + +/* + * USB Suspend Function + * Called automatically on USB Suspend + * Return Value: None + */ + +void USB_Suspend (void) { + /* Performed by Hardware */ +} + + +/* + * USB Resume Function + * Called automatically on USB Resume + * Return Value: None + */ + +void USB_Resume (void) { + /* Performed by Hardware */ +} + + +/* + * USB Remote Wakeup Function + * Called automatically on USB Remote Wakeup + * Return Value: None + */ + +void USB_WakeUp (void) { + + if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP) { + WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); + } +} + + +/* + * USB Remote Wakeup Configuration Function + * Parameters: cfg: Enable/Disable + * Return Value: None + */ + +void USB_WakeUpCfg (uint32_t cfg) { + cfg = cfg; /* Not needed */ +} + + +/* + * USB Set Address Function + * Parameters: adr: USB Address + * Return Value: None + */ + +void USB_SetAddress (uint32_t adr) { + WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Don't wait for next */ + WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Setup Status Phase */ +} + + +/* + * USB Configure Function + * Parameters: cfg: Configure/Deconfigure + * Return Value: None + */ + +void USB_Configure (uint32_t cfg) { + + WrCmdDat(CMD_CFG_DEV, DAT_WR_BYTE(cfg ? CONF_DVICE : 0)); + return; +} + + +/* + * Configure USB Endpoint according to Descriptor + * Parameters: pEPD: Pointer to Endpoint Descriptor + * Return Value: None + */ + +void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) { + return; +} + + +/* + * Set Direction for USB Control Endpoint + * Parameters: dir: Out (dir == 0), In (dir <> 0) + * Return Value: None + */ + +void USB_DirCtrlEP (uint32_t dir) { + dir = dir; /* Not needed */ +} + + +/* + * Enable USB Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USB_EnableEP (uint32_t EPNum) { + WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0)); +} + + +/* + * Disable USB Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USB_DisableEP (uint32_t EPNum) { + WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_DA)); +} + + +/* + * Reset USB Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USB_ResetEP (uint32_t EPNum) { + WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0)); +} + + +/* + * Set Stall for USB Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USB_SetStallEP (uint32_t EPNum) { + WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_ST)); +} + + +/* + * Clear Stall for USB Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USB_ClrStallEP (uint32_t EPNum) { + WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0)); +} + + +/* + * Clear USB Endpoint Buffer + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USB_ClearEPBuf (uint32_t EPNum) { + WrCmdEP(EPNum, CMD_CLR_BUF); +} + + +/* + * Read USB Endpoint Data + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * Return Value: Number of bytes read + */ + +uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData) { + uint32_t cnt, n; + + LPC_USB->Ctrl = ((EPNum & 0x0F) << 2) | CTRL_RD_EN; + /* 3 clock cycles to fetch the packet length from RAM. */ + delay( 5 ); + + do { + cnt = LPC_USB->RxPLen; + } while ((cnt & PKT_DV) == 0); + cnt &= PKT_LNGTH_MASK; + + for (n = 0; n < (cnt + 3) / 4; n++) { + *((uint32_t __attribute__((packed)) *)pData) = LPC_USB->RxData; + pData += 4; + } + + LPC_USB->Ctrl = 0; + + if ((EPNum & 0x80) != 0x04) { /* Non-Isochronous Endpoint */ + WrCmdEP(EPNum, CMD_CLR_BUF); + } + + return (cnt); +} + + +/* + * Write USB Endpoint Data + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * cnt: Number of bytes to write + * Return Value: Number of bytes written + */ + +uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) { + uint32_t n; + + LPC_USB->Ctrl = ((EPNum & 0x0F) << 2) | CTRL_WR_EN; + /* 3 clock cycles to fetch the packet length from RAM. */ + delay( 5 ); + LPC_USB->TxPLen = cnt; + + for (n = 0; n < (cnt + 3) / 4; n++) { + LPC_USB->TxData = *((uint32_t __attribute__((packed)) *)pData); + pData += 4; + } + + LPC_USB->Ctrl = 0; + + WrCmdEP(EPNum, CMD_VALID_BUF); + + return (cnt); +} + +/* + * Get USB Last Frame Number + * Parameters: None + * Return Value: Frame Number + */ + +uint32_t USB_GetFrame (void) { + uint32_t val; + + WrCmd(CMD_RD_FRAME); + val = RdCmdDat(DAT_RD_FRAME); + val = val | (RdCmdDat(DAT_RD_FRAME) << 8); + + return (val); +} + + +/* + * USB Interrupt Service Routine + */ + +void USB_IRQHandler (void) +{ + uint32_t disr, val, n, m; + + disr = LPC_USB->DevIntSt; /* Device Interrupt Status */ + LPC_USB->DevIntClr = disr; + + /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */ + if (disr & DEV_STAT_INT) { + WrCmd(CMD_GET_DEV_STAT); + val = RdCmdDat(DAT_GET_DEV_STAT); /* Device Status */ + if (val & DEV_RST) { /* Reset */ + USB_Reset(); +#if USB_RESET_EVENT + USB_Reset_Event(); +#endif + } + if (val & DEV_CON_CH) { /* Connect change */ +#if USB_POWER_EVENT + USB_Power_Event(val & DEV_CON); +#endif + } + if (val & DEV_SUS_CH) { /* Suspend/Resume */ + if (val & DEV_SUS) { /* Suspend */ + USB_Suspend(); +#if USB_SUSPEND_EVENT + USB_Suspend_Event(); +#endif + } else { /* Resume */ + USB_Resume(); +#if USB_RESUME_EVENT + USB_Resume_Event(); +#endif + } + } + goto isr_end; + } + +#if USB_SOF_EVENT + /* Start of Frame Interrupt */ + if (disr & FRAME_INT) { + LPC_USB->DevIntClr = FRAME_INT; + USB_SOF_Event(); + SOFIRQCount++; + } +#endif + +#if USB_ERROR_EVENT + /* NO error interrupt anymore, below code can be used + as example to get error status from command engine. */ + /* Error Interrupt */ + if (disr & ERR_INT) { + WrCmd(CMD_RD_ERR_STAT); + val = RdCmdDat(DAT_RD_ERR_STAT); + USB_Error_Event(val); + } +#endif + + /* Endpoint's Interrupt */ + if (disr & (0xFF<<1)) { + /* if any of the EP0 through EP7 is set, or bit 1 through 9 on disr */ + for (n = 0; n < USB_EP_NUM; n++) { /* Check All Endpoints */ + /* skip frame interrupt at bit 0 in disr */ +// if (disr & ((1 << n)<<1)) { + if ((disr>>1) & (1 << n)) { + m = n >> 1; + /* clear EP interrupt by sending cmd to the command engine. */ + WrCmd(CMD_SEL_EP_CLRI(n)); + val = RdCmdDat(DAT_SEL_EP_CLRI(n)); + if ((n & 1) == 0) { /* OUT Endpoint */ + if (n == 0) { /* Control OUT Endpoint */ + if (val & EP_SEL_STP) { /* Setup Packet */ + if (USB_P_EP[0]) { + USB_P_EP[0](USB_EVT_SETUP); + continue; + } + } + } + if (USB_P_EP[m]) { + USB_P_EP[m](USB_EVT_OUT); + } + } else { /* IN Endpoint */ + if (USB_P_EP[m]) { + USB_P_EP[m](USB_EVT_IN); + } + } + } + } + } +isr_end: + return; +} diff --git a/firmware/usbcomp_msd_cdc/src/usbuser.c b/firmware/usbcomp_msd_cdc/src/usbuser.c index a6c3a5e..c13556d 100644 --- a/firmware/usbcomp_msd_cdc/src/usbuser.c +++ b/firmware/usbcomp_msd_cdc/src/usbuser.c @@ -1,217 +1,217 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbuser.c - * Purpose: USB Custom User Module - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ -#include "type.h" - -#include "usb.h" -#include "usbcfg.h" -#include "usbhw.h" -#include "usbcore.h" -#include "usbuser.h" -#include "cdcuser.h" -#include "mscuser.h" -#include "memory.h" - - -/* - * USB Power Event Callback - * Called automatically on USB Power Event - * Parameter: power: On(TRUE)/Off(FALSE) - */ - -#if USB_POWER_EVENT -void USB_Power_Event (uint32_t power) { -} -#endif - - -/* - * USB Reset Event Callback - * Called automatically on USB Reset Event - */ - -#if USB_RESET_EVENT -void USB_Reset_Event (void) { - USB_ResetCore(); -} -#endif - - -/* - * USB Suspend Event Callback - * Called automatically on USB Suspend Event - */ - -#if USB_SUSPEND_EVENT -void USB_Suspend_Event (void) { -} -#endif - - -/* - * USB Resume Event Callback - * Called automatically on USB Resume Event - */ - -#if USB_RESUME_EVENT -void USB_Resume_Event (void) { -} -#endif - - -/* - * USB Remote Wakeup Event Callback - * Called automatically on USB Remote Wakeup Event - */ - -#if USB_WAKEUP_EVENT -void USB_WakeUp_Event (void) { -} -#endif - - -/* - * USB Start of Frame Event Callback - * Called automatically on USB Start of Frame Event - */ - -#if USB_SOF_EVENT -void USB_SOF_Event (void) { -} -#endif - - -/* - * USB Error Event Callback - * Called automatically on USB Error Event - * Parameter: error: Error Code - */ - -#if USB_ERROR_EVENT -void USB_Error_Event (uint32_t error) { -} -#endif - - -/* - * USB Set Configuration Event Callback - * Called automatically on USB Set Configuration Request - */ - -#if USB_CONFIGURE_EVENT -void USB_Configure_Event (void) { - - if (USB_Configuration) { /* Check if USB is configured */ - /* add your code here */ - } -} -#endif - - -/* - * USB Set Interface Event Callback - * Called automatically on USB Set Interface Request - */ - -#if USB_INTERFACE_EVENT -void USB_Interface_Event (void) { -} -#endif - - -/* - * USB Set/Clear Feature Event Callback - * Called automatically on USB Set/Clear Feature Request - */ - -#if USB_FEATURE_EVENT -void USB_Feature_Event (void) { -} -#endif - - -#define P_EP(n) ((USB_EP_EVENT & (1 << (n))) ? USB_EndPoint##n : NULL) - -/* USB Endpoint Events Callback Pointers */ -void (* const USB_P_EP[USB_LOGIC_EP_NUM]) (uint32_t event) = { - P_EP(0), - P_EP(1), - P_EP(2), - P_EP(3), - P_EP(4), -}; - - -/* - * USB Endpoint 1 Event Callback - * Called automatically on USB Endpoint 1 Event - * Parameter: event - */ - -void USB_EndPoint1 (uint32_t event) { - uint16_t temp; - static uint16_t serialState; - - switch (event) { - case USB_EVT_IN: - temp = CDC_GetSerialState(); - if (serialState != temp) { - serialState = temp; - CDC_NotificationIn(); /* send SERIAL_STATE notification */ - } - break; - } -} - - -/* - * USB Endpoint 2 Event Callback - * Called automatically on USB Endpoint 2 Event - * Parameter: event - */ - -void USB_EndPoint2 (uint32_t event) { - - switch (event) { - case USB_EVT_OUT: - MSC_BulkOut(); - break; - case USB_EVT_IN: - MSC_BulkIn(); - break; - } -} - - -/* - * USB Endpoint 3 Event Callback - * Called automatically on USB Endpoint 3 Event - * Parameter: event - */ - -void USB_EndPoint3 (uint32_t event) { - switch (event) { - case USB_EVT_OUT: - CDC_BulkOut (); /* data received from Host */ - break; - case USB_EVT_IN: - CDC_BulkIn (); /* data expected from Host */ - break; - } -} - - +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbuser.c + * Purpose: USB Custom User Module + * Version: V1.20 + *---------------------------------------------------------------------------- + * This software is supplied "AS IS" without any warranties, express, + * implied or statutory, including but not limited to the implied + * warranties of fitness for purpose, satisfactory quality and + * noninfringement. Keil extends you a royalty-free right to reproduce + * and distribute executable files created using this software for use + * on NXP Semiconductors LPC microcontroller devices only. Nothing else + * gives you the right to use this software. + * + * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#include "type.h" + +#include "usb.h" +#include "usbcfg.h" +#include "usbhw.h" +#include "usbcore.h" +#include "usbuser.h" +#include "cdcuser.h" +#include "mscuser.h" +#include "memory.h" + + +/* + * USB Power Event Callback + * Called automatically on USB Power Event + * Parameter: power: On(TRUE)/Off(FALSE) + */ + +#if USB_POWER_EVENT +void USB_Power_Event (uint32_t power) { +} +#endif + + +/* + * USB Reset Event Callback + * Called automatically on USB Reset Event + */ + +#if USB_RESET_EVENT +void USB_Reset_Event (void) { + USB_ResetCore(); +} +#endif + + +/* + * USB Suspend Event Callback + * Called automatically on USB Suspend Event + */ + +#if USB_SUSPEND_EVENT +void USB_Suspend_Event (void) { +} +#endif + + +/* + * USB Resume Event Callback + * Called automatically on USB Resume Event + */ + +#if USB_RESUME_EVENT +void USB_Resume_Event (void) { +} +#endif + + +/* + * USB Remote Wakeup Event Callback + * Called automatically on USB Remote Wakeup Event + */ + +#if USB_WAKEUP_EVENT +void USB_WakeUp_Event (void) { +} +#endif + + +/* + * USB Start of Frame Event Callback + * Called automatically on USB Start of Frame Event + */ + +#if USB_SOF_EVENT +void USB_SOF_Event (void) { +} +#endif + + +/* + * USB Error Event Callback + * Called automatically on USB Error Event + * Parameter: error: Error Code + */ + +#if USB_ERROR_EVENT +void USB_Error_Event (uint32_t error) { +} +#endif + + +/* + * USB Set Configuration Event Callback + * Called automatically on USB Set Configuration Request + */ + +#if USB_CONFIGURE_EVENT +void USB_Configure_Event (void) { + + if (USB_Configuration) { /* Check if USB is configured */ + /* add your code here */ + } +} +#endif + + +/* + * USB Set Interface Event Callback + * Called automatically on USB Set Interface Request + */ + +#if USB_INTERFACE_EVENT +void USB_Interface_Event (void) { +} +#endif + + +/* + * USB Set/Clear Feature Event Callback + * Called automatically on USB Set/Clear Feature Request + */ + +#if USB_FEATURE_EVENT +void USB_Feature_Event (void) { +} +#endif + + +#define P_EP(n) ((USB_EP_EVENT & (1 << (n))) ? USB_EndPoint##n : NULL) + +/* USB Endpoint Events Callback Pointers */ +void (* const USB_P_EP[USB_LOGIC_EP_NUM]) (uint32_t event) = { + P_EP(0), + P_EP(1), + P_EP(2), + P_EP(3), + P_EP(4), +}; + + +/* + * USB Endpoint 1 Event Callback + * Called automatically on USB Endpoint 1 Event + * Parameter: event + */ + +void USB_EndPoint1 (uint32_t event) { + uint16_t temp; + static uint16_t serialState; + + switch (event) { + case USB_EVT_IN: + temp = CDC_GetSerialState(); + if (serialState != temp) { + serialState = temp; + CDC_NotificationIn(); /* send SERIAL_STATE notification */ + } + break; + } +} + + +/* + * USB Endpoint 2 Event Callback + * Called automatically on USB Endpoint 2 Event + * Parameter: event + */ + +void USB_EndPoint2 (uint32_t event) { + + switch (event) { + case USB_EVT_OUT: + MSC_BulkOut(); + break; + case USB_EVT_IN: + MSC_BulkIn(); + break; + } +} + + +/* + * USB Endpoint 3 Event Callback + * Called automatically on USB Endpoint 3 Event + * Parameter: event + */ + +void USB_EndPoint3 (uint32_t event) { + switch (event) { + case USB_EVT_OUT: + CDC_BulkOut (); /* data received from Host */ + break; + case USB_EVT_IN: + CDC_BulkIn (); /* data expected from Host */ + break; + } +} + +