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Pavol Rusnak
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1 changed files with 118 additions and 118 deletions
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/****************************************************************************
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* $Id:: ssp.h 3632 2010-06-01 22:54:42Z usb00423 $
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* Project: NXP LPC13xx SSP example
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*
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* Description:
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* This file contains SSP code header definition.
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*
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****************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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****************************************************************************/
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#ifndef __SSP_H__
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#define __SSP_H__
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/* There are there modes in SSP: loopback, master or slave. */
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/* Here are the combination of all the tests.
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(1) LOOPBACK test: LOOPBACK_MODE=1, TX_RX_ONLY=0, USE_CS=1;
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(2) Serial EEPROM test: LOOPBACK_MODE=0, TX_RX_ONLY=0, USE_CS=0; (default)
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(3) TX(Master) Only: LOOPBACK_MODE=0, SSP_SLAVE=0, TX_RX_ONLY=1, USE_CS=1;
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(4) RX(Slave) Only: LOOPBACK_MODE=0, SSP_SLAVE=1, TX_RX_ONLY=0, USE_CS=1 */
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#define LOOPBACK_MODE 0 /* 1 is loopback, 0 is normal operation. */
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#define SSP_SLAVE 0 /* 1 is SLAVE mode, 0 is master mode */
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#define TX_RX_ONLY 0 /* 1 is TX or RX only depending on SSP_SLAVE
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flag, 0 is either loopback mode or communicate
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with a serial EEPROM. */
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/* if USE_CS is zero, set SSEL as GPIO that you have total control of the sequence */
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/* When test serial SEEPROM(LOOPBACK_MODE=0, TX_RX_ONLY=0), set USE_CS to 0. */
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/* When LOOPBACK_MODE=1 or TX_RX_ONLY=1, set USE_CS to 1. */
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#define USE_CS 0
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#define SSP_DEBUG 0
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/* SPI read and write buffer size */
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#define SSP_BUFSIZE 16
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#define FIFOSIZE 8
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#define DELAY_COUNT 10
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#define MAX_TIMEOUT 0xFF
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/* Port0.2 is the SSP select pin */
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#define SSP0_SEL (0x1<<2)
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/* SSP Status register */
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#define SSPSR_TFE (0x1<<0)
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#define SSPSR_TNF (0x1<<1)
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#define SSPSR_RNE (0x1<<2)
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#define SSPSR_RFF (0x1<<3)
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#define SSPSR_BSY (0x1<<4)
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/* SSP CR0 register */
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#define SSPCR0_DSS (0x1<<0)
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#define SSPCR0_FRF (0x1<<4)
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#define SSPCR0_SPO (0x1<<6)
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#define SSPCR0_SPH (0x1<<7)
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#define SSPCR0_SCR (0x1<<8)
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/* SSP CR1 register */
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#define SSPCR1_LBM (0x1<<0)
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#define SSPCR1_SSE (0x1<<1)
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#define SSPCR1_MS (0x1<<2)
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#define SSPCR1_SOD (0x1<<3)
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/* SSP Interrupt Mask Set/Clear register */
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#define SSPIMSC_RORIM (0x1<<0)
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#define SSPIMSC_RTIM (0x1<<1)
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#define SSPIMSC_RXIM (0x1<<2)
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#define SSPIMSC_TXIM (0x1<<3)
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/* SSP0 Interrupt Status register */
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#define SSPRIS_RORRIS (0x1<<0)
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#define SSPRIS_RTRIS (0x1<<1)
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#define SSPRIS_RXRIS (0x1<<2)
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#define SSPRIS_TXRIS (0x1<<3)
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/* SSP0 Masked Interrupt register */
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#define SSPMIS_RORMIS (0x1<<0)
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#define SSPMIS_RTMIS (0x1<<1)
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#define SSPMIS_RXMIS (0x1<<2)
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#define SSPMIS_TXMIS (0x1<<3)
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/* SSP0 Interrupt clear register */
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#define SSPICR_RORIC (0x1<<0)
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#define SSPICR_RTIC (0x1<<1)
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/* ATMEL SEEPROM command set */
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#define WREN 0x06 /* MSB A8 is set to 0, simplifying test */
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#define WRDI 0x04
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#define RDSR 0x05
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#define WRSR 0x01
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#define READ 0x03
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#define WRITE 0x02
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/* RDSR status bit definition */
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#define RDSR_RDY 0x01
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#define RDSR_WEN 0x02
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/* If RX_INTERRUPT is enabled, the SSP RX will be handled in the ISR
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SSPReceive() will not be needed. */
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extern void SSP_IRQHandler (void);
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extern void SSPInit( void );
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extern void SSPSend( char *Buf, uint32_t Length );
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extern void SSPReceive( uint8_t *buf, uint32_t Length );
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#endif /* __SSP_H__ */
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/*****************************************************************************
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** End Of File
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******************************************************************************/
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/****************************************************************************
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* $Id:: ssp.h 3632 2010-06-01 22:54:42Z usb00423 $
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* Project: NXP LPC13xx SSP example
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*
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* Description:
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* This file contains SSP code header definition.
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*
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****************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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****************************************************************************/
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#ifndef __SSP_H__
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#define __SSP_H__
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/* There are there modes in SSP: loopback, master or slave. */
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/* Here are the combination of all the tests.
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(1) LOOPBACK test: LOOPBACK_MODE=1, TX_RX_ONLY=0, USE_CS=1;
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(2) Serial EEPROM test: LOOPBACK_MODE=0, TX_RX_ONLY=0, USE_CS=0; (default)
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(3) TX(Master) Only: LOOPBACK_MODE=0, SSP_SLAVE=0, TX_RX_ONLY=1, USE_CS=1;
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(4) RX(Slave) Only: LOOPBACK_MODE=0, SSP_SLAVE=1, TX_RX_ONLY=0, USE_CS=1 */
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#define LOOPBACK_MODE 0 /* 1 is loopback, 0 is normal operation. */
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#define SSP_SLAVE 0 /* 1 is SLAVE mode, 0 is master mode */
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#define TX_RX_ONLY 0 /* 1 is TX or RX only depending on SSP_SLAVE
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flag, 0 is either loopback mode or communicate
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with a serial EEPROM. */
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/* if USE_CS is zero, set SSEL as GPIO that you have total control of the sequence */
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/* When test serial SEEPROM(LOOPBACK_MODE=0, TX_RX_ONLY=0), set USE_CS to 0. */
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/* When LOOPBACK_MODE=1 or TX_RX_ONLY=1, set USE_CS to 1. */
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#define USE_CS 0
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#define SSP_DEBUG 0
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/* SPI read and write buffer size */
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#define SSP_BUFSIZE 16
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#define FIFOSIZE 8
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#define DELAY_COUNT 10
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#define MAX_TIMEOUT 0xFF
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/* Port0.2 is the SSP select pin */
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#define SSP0_SEL (0x1<<2)
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/* SSP Status register */
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#define SSPSR_TFE (0x1<<0)
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#define SSPSR_TNF (0x1<<1)
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#define SSPSR_RNE (0x1<<2)
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#define SSPSR_RFF (0x1<<3)
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#define SSPSR_BSY (0x1<<4)
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/* SSP CR0 register */
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#define SSPCR0_DSS (0x1<<0)
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#define SSPCR0_FRF (0x1<<4)
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#define SSPCR0_SPO (0x1<<6)
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#define SSPCR0_SPH (0x1<<7)
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#define SSPCR0_SCR (0x1<<8)
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/* SSP CR1 register */
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#define SSPCR1_LBM (0x1<<0)
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#define SSPCR1_SSE (0x1<<1)
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#define SSPCR1_MS (0x1<<2)
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#define SSPCR1_SOD (0x1<<3)
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/* SSP Interrupt Mask Set/Clear register */
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#define SSPIMSC_RORIM (0x1<<0)
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#define SSPIMSC_RTIM (0x1<<1)
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#define SSPIMSC_RXIM (0x1<<2)
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#define SSPIMSC_TXIM (0x1<<3)
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/* SSP0 Interrupt Status register */
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#define SSPRIS_RORRIS (0x1<<0)
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#define SSPRIS_RTRIS (0x1<<1)
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#define SSPRIS_RXRIS (0x1<<2)
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#define SSPRIS_TXRIS (0x1<<3)
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/* SSP0 Masked Interrupt register */
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#define SSPMIS_RORMIS (0x1<<0)
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#define SSPMIS_RTMIS (0x1<<1)
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#define SSPMIS_RXMIS (0x1<<2)
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#define SSPMIS_TXMIS (0x1<<3)
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/* SSP0 Interrupt clear register */
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#define SSPICR_RORIC (0x1<<0)
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#define SSPICR_RTIC (0x1<<1)
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/* ATMEL SEEPROM command set */
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#define WREN 0x06 /* MSB A8 is set to 0, simplifying test */
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#define WRDI 0x04
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#define RDSR 0x05
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#define WRSR 0x01
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#define READ 0x03
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#define WRITE 0x02
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/* RDSR status bit definition */
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#define RDSR_RDY 0x01
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#define RDSR_WEN 0x02
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/* If RX_INTERRUPT is enabled, the SSP RX will be handled in the ISR
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SSPReceive() will not be needed. */
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extern void SSP_IRQHandler (void);
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extern void SSPInit( void );
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extern void SSPSend( char *Buf, uint32_t Length );
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extern void SSPReceive( uint8_t *buf, uint32_t Length );
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#endif /* __SSP_H__ */
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/*****************************************************************************
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** End Of File
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******************************************************************************/
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