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This commit is contained in:
BIITER 2011-04-27 00:06:22 +02:00
parent e38d475d40
commit af36fa43f0
8 changed files with 57 additions and 36 deletions
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10
firmware/src/LPC13xx.h
View file

@ -238,18 +238,18 @@ typedef struct
__IO uint32_t PIO0_8;
__IO uint32_t PIO0_9;
__IO uint32_t JTAG_TCK_PIO0_10;
__IO uint32_t PIO0_10;
__IO uint32_t PIO1_10;
__IO uint32_t PIO2_11;
__IO uint32_t PIO0_11; // JTAG_TDI_PIO0_11
__IO uint32_t JTAG_TMS_PIO1_0;
__IO uint32_t JTAG_TDO_PIO1_1;
__IO uint32_t PIO1_0;
__IO uint32_t PIO1_1;
__IO uint32_t JTAG_nTRST_PIO1_2;
__IO uint32_t PIO1_2;
__IO uint32_t PIO3_0;
__IO uint32_t PIO3_1;
__IO uint32_t PIO2_3;
__IO uint32_t ARM_SWDIO_PIO1_3;
__IO uint32_t PIO1_3;
__IO uint32_t PIO1_4;
__IO uint32_t PIO1_11;
__IO uint32_t PIO3_2;

24
firmware/src/adc.c
View file

@ -160,26 +160,22 @@ void ADCInit( uint32_t ADC_Clk )
to design team. */
LPC_IOCON->PIO0_11 &= ~0x8F; /* ADC I/O config */
LPC_IOCON->PIO0_11 |= 0x02; /* ADC IN0 */
#ifdef __JTAG_DISABLED
LPC_IOCON->R_PIO1_0 &= ~0x8F;
LPC_IOCON->R_PIO1_0 |= 0x02; /* ADC IN1 */
LPC_IOCON->R_PIO1_1 &= ~0x8F;
LPC_IOCON->R_PIO1_1 |= 0x02; /* ADC IN2 */
LPC_IOCON->R_PIO1_2 &= ~0x8F;
LPC_IOCON->R_PIO1_2 |= 0x02; /* ADC IN3 */
#ifdef __SWD_DISABLED
LPC_IOCON->SWDIO_PIO1_3 &= ~0x8F;
LPC_IOCON->SWDIO_PIO1_3 |= 0x02; /* ADC IN4 */
#endif
#endif
#if 0
LPC_IOCON->PIO1_0 &= ~0x8F;
LPC_IOCON->PIO1_0 |= 0x02; /* ADC IN1 */
LPC_IOCON->PIO1_1 &= ~0x8F;
LPC_IOCON->PIO1_1 |= 0x02; /* ADC IN2 */
LPC_IOCON->PIO1_2 &= ~0x8F;
LPC_IOCON->PIO1_2 |= 0x02; /* ADC IN3 */
LPC_IOCON->PIO1_3 &= ~0x8F;
LPC_IOCON->PIO1_3 |= 0x02; /* ADC IN4 */
LPC_IOCON->PIO1_4 &= ~0x8F; /* Clear bit7, change to analog mode. */
LPC_IOCON->PIO1_4 |= 0x01; /* ADC IN5 */
LPC_IOCON->PIO1_10 &= ~0x8F; /* Clear bit7, change to analog mode. */
LPC_IOCON->PIO1_10 |= 0x01; /* ADC IN6 */
LPC_IOCON->PIO1_11 &= ~0x8F; /* Clear bit7, change to analog mode. */
LPC_IOCON->PIO1_11 |= 0x01; /* ADC IN7 */
#endif
LPC_ADC->CR = ( 0x01 << 0 ) | /* SEL=1,select channel 0~7 on ADC0 */
(((SystemCoreClock/LPC_SYSCON->SYSAHBCLKDIV)/ADC_Clk-1)<<8) | /* CLKDIV = Fpclk / 1000000 - 1 */

40
firmware/src/edubrm.c
View file

@ -15,9 +15,11 @@ void GetInReport (uint8_t src[], uint32_t length)
src[i*2 ] = v & 0xff;
src[i*2+1] = (v>>8) & 0xff;
}
// TODO: fix the following - replace IP[i] with real value of input pin (I)
// src[14] = IP[0] + (IP[1]<<1) + (IP[2]<<2);
src[14] = 0;
src[14] |= (LPC_GPIO2->MASKED_ACCESS[1<<0] & (1<<0));
src[14] |= (LPC_GPIO2->MASKED_ACCESS[1<<6] & (1<<6));
src[14] |= (LPC_GPIO2->MASKED_ACCESS[1<<7] & (1<<7));
}
void SetOutReport (uint8_t dst[], uint32_t length)
@ -82,22 +84,44 @@ void SetOutReport (uint8_t dst[], uint32_t length)
}
}
void PinInit() {
PinDir(0); // all 3 pins are output 0
PinState(1, 0);
PinState(2, 0);
PinState(3, 0);
}
void EduInit() {
SSPInit();
ADCInit(ADC_CLK);
PinInit();
}
void PinDir(uint16_t mask) {
mask &= 7;
mask ^= 7;
mask = ((mask & 4) << 5) | ((mask & 2) << 5) | (mask & 1);
LPC_GPIO2->DIR |= mask;
mask |= ~(1<<0 | 1<<6 | 1<<7);
LPC_GPIO2->DIR &= mask;
LPC_GPIO2->MASKED_ACCESS[1<<0] |= 1<<0;
LPC_GPIO2->MASKED_ACCESS[1<<6] |= 1<<6;
LPC_GPIO2->MASKED_ACCESS[1<<7] |= 1<<7;
if (!(mask & 1))
PinState(1, 0);
if (!(mask & (1<<6)))
PinState(2, 0);
if (!(mask & (1<<7)))
PinState(3, 0);
}
void PinState(uint8_t which, uint8_t state) {
// if (which > 1) which += 4;
// LPC_GPIO2->MASKED_ACCESS[1<<which] |= (1<<which);
// LPC_GPIO2->MASKED_ACCESS[1<<which] &= (1<<which);
state &= 1;
which -= 1;
if (which > 0)which += 5;
LPC_GPIO2->MASKED_ACCESS[1<<which] |= (state<<which);
LPC_GPIO2->MASKED_ACCESS[1<<which] &= ((state<<which) | ~(1<<which));
}
void TIMER16_1_IRQHandler(void) {

2
firmware/src/edubrm.h
View file

@ -3,3 +3,5 @@ void SetOutReport (uint8_t dst[], uint32_t length);
void EnablePWM1(uint32_t period, uint32_t duty);
void EnablePWM2(uint16_t period, uint16_t duty);
void PinDir(uint16_t mask);
void PinState(uint8_t which, uint8_t state);
void EduInit();

5
firmware/src/ssp.c
View file

@ -27,7 +27,6 @@ void SSPSend( const uint8_t *buf, uint32_t Length )
}
void SSPInit() {
uint32_t i;
// reset peripherals
LPC_SYSCON->PRESETCTRL |= (0x01<<0); // SSP reset de-asserted
@ -73,6 +72,8 @@ LPC_SSP->CR1 = (0x01<<1) | (0x00<<2);
/* enable all error related interrupts */
LPC_SSP->IMSC = (0x1<<0) | (0x1<<1);
/* old debug display routine
* uint32_t i;
// command
LPC_GPIO0->MASKED_ACCESS[0x01<<7] = 0 << 7;
@ -87,5 +88,5 @@ LPC_GPIO0->MASKED_ACCESS[0x01<<7] = 1 << 7;
// clear display
for (i=0;i<84*6;i++)
SSPSend((uint8_t *)"\x00", 1);
*/
}

8
firmware/src/usbhidrom_main.c
View file

@ -43,12 +43,8 @@ int main (void)
SystemInit();
//#endif
SSPInit();
ADCInit(ADC_CLK);
// enable read on pin PIO3_3
LPC_GPIO3->DIR &= ~(1<<3);
// LPC_GPIO3->DIR &= ~(1<<3);
HidDevInfo.idVendor = USB_VENDOR_ID;
HidDevInfo.idProduct = USB_PROD_ID;
@ -89,6 +85,8 @@ int main (void)
LPC_GPIO2->MASKED_ACCESS[1<<6] |= 1<<6;
LPC_GPIO2->MASKED_ACCESS[1<<7] |= 1<<7;
EduInit();
while (1)
__WFI();
}

2
software/device.py
View file

@ -79,7 +79,7 @@ class Device:
if self.fake:
print 'setout', which, state
else:
self.epo.write('o' + chr(which<<1 + state))
self.epo.write('o' + chr((which<<1) + state))
# 7x AD (16 bits) + 3 x I
def read(self):

2
software/modules/ModuleDebug.py
View file

@ -29,7 +29,7 @@ class ModuleDebugWidget(QWidget):
# real device:
self.dev = Device()
# fake device:
# self.dev = Device(True)
# self.dev = Device(True)
self.timer = QTimer()
QObject.connect(self.timer, SIGNAL("timeout()"), self.read_inputs)