mirror of
https://github.com/brmlab/edubrm.git
synced 2025-12-16 18:43:58 +01:00
cleanup phase #1
This commit is contained in:
Pavol Rusnak
parent
66287a6f3a
commit
c3ff2207cd
46 changed files with 11677 additions and 13637 deletions
File diff suppressed because it is too large
Load diff
|
|
@ -1,81 +1,81 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>CMSISv1p30_LPC13xx</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>make</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${workspace_loc:/CMSISv1p30_LPC13xx/Debug}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>CMSISv1p30_LPC13xx</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>make</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${workspace_loc:/CMSISv1p30_LPC13xx/Debug}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
|
|
|
|||
|
|
@ -1,28 +1,28 @@
|
|||
CMSIS : Cortex Microcontroller Software Interface Standard
|
||||
==========================================================
|
||||
CMSIS defines for a Cortex-M Microcontroller System:
|
||||
|
||||
* A common way to access peripheral registers and a
|
||||
common way to define exception vectors.
|
||||
* The register names of the Core Peripherals and the
|
||||
names of the Core Exception Vectors.
|
||||
* An device independent interface for RTOS Kernels
|
||||
including a debug channel.
|
||||
|
||||
By using CMSIS compliant software components, the user can
|
||||
easier re-use template code. CMSIS is intended to enable the
|
||||
combination of software components from multiple middleware
|
||||
vendors.
|
||||
|
||||
This project contains appropriate files for this MCU family
|
||||
taken from CMSIS. A full copy of the CMSIS files can be found
|
||||
within your tools installation directory. More information on
|
||||
CMSIS can be found at:
|
||||
|
||||
http://www.onarm.com/
|
||||
http://www.arm.com/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
CMSIS : Cortex Microcontroller Software Interface Standard
|
||||
==========================================================
|
||||
CMSIS defines for a Cortex-M Microcontroller System:
|
||||
|
||||
* A common way to access peripheral registers and a
|
||||
common way to define exception vectors.
|
||||
* The register names of the Core Peripherals and the
|
||||
names of the Core Exception Vectors.
|
||||
* An device independent interface for RTOS Kernels
|
||||
including a debug channel.
|
||||
|
||||
By using CMSIS compliant software components, the user can
|
||||
easier re-use template code. CMSIS is intended to enable the
|
||||
combination of software components from multiple middleware
|
||||
vendors.
|
||||
|
||||
This project contains appropriate files for this MCU family
|
||||
taken from CMSIS. A full copy of the CMSIS files can be found
|
||||
within your tools installation directory. More information on
|
||||
CMSIS can be found at:
|
||||
|
||||
http://www.onarm.com/
|
||||
http://www.arm.com/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,320 +0,0 @@
|
|||
<html>
|
||||
|
||||
<head>
|
||||
<title>CMSIS Changes</title>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
|
||||
<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
|
||||
<meta name="ProgId" content="FrontPage.Editor.Document">
|
||||
<style>
|
||||
<!--
|
||||
/*-----------------------------------------------------------
|
||||
Keil Software CHM Style Sheet
|
||||
-----------------------------------------------------------*/
|
||||
body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family:
|
||||
Verdana, Arial, 'Sans Serif' }
|
||||
a:link { color: #0000FF; text-decoration: underline }
|
||||
a:visited { color: #0000FF; text-decoration: underline }
|
||||
a:active { color: #FF0000; text-decoration: underline }
|
||||
a:hover { color: #FF0000; text-decoration: underline }
|
||||
h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold;
|
||||
text-align: Center; margin-right: 3 }
|
||||
h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold;
|
||||
background-color: #CCCCCC; margin-top: 24; margin-bottom: 3;
|
||||
padding: 6 }
|
||||
h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color:
|
||||
#CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
|
||||
pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC;
|
||||
margin-left: 24; margin-right: 24 }
|
||||
ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
|
||||
ol { margin-top: 6pt; margin-bottom: 0 }
|
||||
li { clear: both; margin-bottom: 6pt }
|
||||
table { font-size: 100%; border-width: 0; padding: 0 }
|
||||
th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align:
|
||||
bottom; padding-right: 6pt }
|
||||
tr { text-align: left; vertical-align: top }
|
||||
td { text-align: left; vertical-align: top; padding-right: 6pt }
|
||||
.ToolT { font-size: 8pt; color: #808080 }
|
||||
.TinyT { font-size: 8pt; text-align: Center }
|
||||
code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier;
|
||||
line-height: 120%; font-style: normal }
|
||||
/*-----------------------------------------------------------
|
||||
Notes
|
||||
-----------------------------------------------------------*/
|
||||
p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
|
||||
/*-----------------------------------------------------------
|
||||
Expanding/Contracting Divisions
|
||||
-----------------------------------------------------------*/
|
||||
#expand { text-decoration: none; margin-bottom: 3pt }
|
||||
img.expand { border-style: none; border-width: medium }
|
||||
div.expand { display: none; margin-left: 9pt; margin-top: 0 }
|
||||
/*-----------------------------------------------------------
|
||||
Where List Tags
|
||||
-----------------------------------------------------------*/
|
||||
p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
|
||||
table.wh { width: 100% }
|
||||
td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom:
|
||||
6pt }
|
||||
td.whDesc { padding-bottom: 6pt }
|
||||
/*-----------------------------------------------------------
|
||||
Keil Table Tags
|
||||
-----------------------------------------------------------*/
|
||||
table.kt { border: 1pt solid #000000 }
|
||||
th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt;
|
||||
padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
|
||||
tr.kt { }
|
||||
td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0;
|
||||
padding-left: 6pt; padding-right: 6pt; padding-top: 2pt;
|
||||
padding-bottom: 2pt }
|
||||
/*-----------------------------------------------------------
|
||||
-----------------------------------------------------------*/
|
||||
-->
|
||||
|
||||
</style>
|
||||
</head>
|
||||
|
||||
<body>
|
||||
|
||||
<h1>Changes to CMSIS version V1.20</h1>
|
||||
|
||||
<hr>
|
||||
|
||||
<h2>1. Removed CMSIS Middelware packages</h2>
|
||||
<p>
|
||||
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
|
||||
</p>
|
||||
|
||||
<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
|
||||
<p>
|
||||
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
|
||||
because the variable holds the clock value at which the core is running.
|
||||
</p>
|
||||
|
||||
<h2>3. Changed startup concept</h2>
|
||||
<p>
|
||||
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
|
||||
from main) has the weakness that it does not work for controllers which need a already
|
||||
configuerd clock system to configure the external memory controller.
|
||||
</p>
|
||||
|
||||
<h3>Changed startup concept</h3>
|
||||
<ul>
|
||||
<li>
|
||||
SystemInit() is called from startup file before <strong>premain</strong>.
|
||||
</li>
|
||||
<li>
|
||||
<strong>SystemInit()</strong> configures the clock system and also configures
|
||||
an existing external memory controller.
|
||||
</li>
|
||||
<li>
|
||||
<strong>SystemInit()</strong> must not use global variables.
|
||||
</li>
|
||||
<li>
|
||||
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
|
||||
</li>
|
||||
<li>
|
||||
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
|
||||
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
|
||||
and must be called whenever the core clock is changed.<br>
|
||||
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
|
||||
the current core clock.
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h2>4. Advanced Debug Functions</h2>
|
||||
<p>
|
||||
ITM communication channel is only capable for OUT direction. To allow also communication for
|
||||
IN direction a simple concept is provided.
|
||||
</p>
|
||||
<ul>
|
||||
<li>
|
||||
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
|
||||
</li>
|
||||
<li>
|
||||
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
|
||||
</li>
|
||||
<li>
|
||||
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
|
||||
</p>
|
||||
|
||||
|
||||
<h2>5. Core Register Bit Definitions</h2>
|
||||
<p>
|
||||
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
|
||||
defines correspond with the Cortex-M Technical Reference Manual.
|
||||
</p>
|
||||
<p>
|
||||
e.g. SysTick structure with bit definitions
|
||||
</p>
|
||||
<pre>
|
||||
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
|
||||
memory mapped structure for SysTick
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
|
||||
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
|
||||
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
|
||||
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||
/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
|
||||
|
||||
<h2>7. DoxyGen Tags</h2>
|
||||
<p>
|
||||
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
|
||||
using DoxyGen.
|
||||
</p>
|
||||
|
||||
<h2>8. Folder Structure</h2>
|
||||
<p>
|
||||
The folder structure is changed to differentiate the single support packages.
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li>CM0</li>
|
||||
<li>CM3
|
||||
<ul>
|
||||
<li>CoreSupport</li>
|
||||
<li>DeviceSupport</li>
|
||||
<ul>
|
||||
<li>Vendor
|
||||
<ul>
|
||||
<li>Device
|
||||
<ul>
|
||||
<li>Startup
|
||||
<ul>
|
||||
<li>Toolchain</li>
|
||||
<li>Toolchain</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Device</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Vendor</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Example
|
||||
<ul>
|
||||
<li>Toolchain
|
||||
<ul>
|
||||
<li>Device</li>
|
||||
<li>Device</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Toolchain</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</li>
|
||||
|
||||
<li>Documentation</li>
|
||||
</ul>
|
||||
|
||||
<h2>9. Open Points</h2>
|
||||
<p>
|
||||
Following points need to be clarified and solved:
|
||||
</p>
|
||||
<ul>
|
||||
<li>
|
||||
<p>
|
||||
Equivalent C and Assembler startup files.
|
||||
</p>
|
||||
<p>
|
||||
Is there a need for having C startup files although assembler startup files are
|
||||
very efficient and do not need to be changed?
|
||||
<p/>
|
||||
</li>
|
||||
<li>
|
||||
<p>
|
||||
Placing of HEAP in external RAM.
|
||||
</p>
|
||||
<p>
|
||||
It must be possible to place HEAP in external RAM if the device supports an
|
||||
external memory controller.
|
||||
</p>
|
||||
</li>
|
||||
<li>
|
||||
<p>
|
||||
Placing of STACK /HEAP.
|
||||
</p>
|
||||
<p>
|
||||
STACK should always be placed at the end of internal RAM.
|
||||
</p>
|
||||
<p>
|
||||
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
|
||||
</p>
|
||||
</li>
|
||||
<li>
|
||||
<p>
|
||||
Removing core_cm3.c and core_cm0.c.
|
||||
</p>
|
||||
<p>
|
||||
On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
|
||||
appropriate compiler intrinsics.
|
||||
</p>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h2>10. Limitations</h2>
|
||||
<p>
|
||||
The following limitations are not covered with the current CMSIS version:
|
||||
</p>
|
||||
<ul>
|
||||
<li>
|
||||
No <strong>C startup files</strong> for ARM toolchain are provided.
|
||||
</li>
|
||||
<li>
|
||||
No <strong>C startup files</strong> for GNU toolchain are provided.
|
||||
</li>
|
||||
<li>
|
||||
No <strong>C startup files</strong> for IAR toolchain are provided.
|
||||
</li>
|
||||
<li>
|
||||
No <strong>Tasking</strong> projects are provided yet.
|
||||
</li>
|
||||
</ul>
|
||||
|
|
@ -1,243 +0,0 @@
|
|||
<html>
|
||||
|
||||
<head>
|
||||
<title>CMSIS Debug Support</title>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
|
||||
<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
|
||||
<meta name="ProgId" content="FrontPage.Editor.Document">
|
||||
<style>
|
||||
<!--
|
||||
/*-----------------------------------------------------------
|
||||
Keil Software CHM Style Sheet
|
||||
-----------------------------------------------------------*/
|
||||
body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family:
|
||||
Verdana, Arial, 'Sans Serif' }
|
||||
a:link { color: #0000FF; text-decoration: underline }
|
||||
a:visited { color: #0000FF; text-decoration: underline }
|
||||
a:active { color: #FF0000; text-decoration: underline }
|
||||
a:hover { color: #FF0000; text-decoration: underline }
|
||||
h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold;
|
||||
text-align: Center; margin-right: 3 }
|
||||
h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold;
|
||||
background-color: #CCCCCC; margin-top: 24; margin-bottom: 3;
|
||||
padding: 6 }
|
||||
h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color:
|
||||
#CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
|
||||
pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC;
|
||||
margin-left: 24; margin-right: 24 }
|
||||
ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
|
||||
ol { margin-top: 6pt; margin-bottom: 0 }
|
||||
li { clear: both; margin-bottom: 6pt }
|
||||
table { font-size: 100%; border-width: 0; padding: 0 }
|
||||
th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align:
|
||||
bottom; padding-right: 6pt }
|
||||
tr { text-align: left; vertical-align: top }
|
||||
td { text-align: left; vertical-align: top; padding-right: 6pt }
|
||||
.ToolT { font-size: 8pt; color: #808080 }
|
||||
.TinyT { font-size: 8pt; text-align: Center }
|
||||
code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier;
|
||||
line-height: 120%; font-style: normal }
|
||||
/*-----------------------------------------------------------
|
||||
Notes
|
||||
-----------------------------------------------------------*/
|
||||
p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
|
||||
/*-----------------------------------------------------------
|
||||
Expanding/Contracting Divisions
|
||||
-----------------------------------------------------------*/
|
||||
#expand { text-decoration: none; margin-bottom: 3pt }
|
||||
img.expand { border-style: none; border-width: medium }
|
||||
div.expand { display: none; margin-left: 9pt; margin-top: 0 }
|
||||
/*-----------------------------------------------------------
|
||||
Where List Tags
|
||||
-----------------------------------------------------------*/
|
||||
p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
|
||||
table.wh { width: 100% }
|
||||
td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom:
|
||||
6pt }
|
||||
td.whDesc { padding-bottom: 6pt }
|
||||
/*-----------------------------------------------------------
|
||||
Keil Table Tags
|
||||
-----------------------------------------------------------*/
|
||||
table.kt { border: 1pt solid #000000 }
|
||||
th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt;
|
||||
padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
|
||||
tr.kt { }
|
||||
td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0;
|
||||
padding-left: 6pt; padding-right: 6pt; padding-top: 2pt;
|
||||
padding-bottom: 2pt }
|
||||
/*-----------------------------------------------------------
|
||||
-----------------------------------------------------------*/
|
||||
-->
|
||||
|
||||
</style>
|
||||
</head>
|
||||
|
||||
<body>
|
||||
|
||||
<h1>CMSIS Debug Support</h1>
|
||||
|
||||
<hr>
|
||||
|
||||
<h2>Cortex-M3 ITM Debug Access</h2>
|
||||
<p>
|
||||
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
|
||||
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
|
||||
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
|
||||
communication channels are used by CMSIS to output the following information:
|
||||
</p>
|
||||
<ul>
|
||||
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
|
||||
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
|
||||
</ul>
|
||||
|
||||
<h2>Debug IN / OUT functions</h2>
|
||||
<p>CMSIS provides following debug functions:</p>
|
||||
<ul>
|
||||
<li>ITM_SendChar (uses ITM channel 0)</li>
|
||||
<li>ITM_ReceiveChar (uses global variable)</li>
|
||||
<li>ITM_CheckChar (uses global variable)</li>
|
||||
</ul>
|
||||
|
||||
<h3>ITM_SendChar</h3>
|
||||
<p>
|
||||
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
|
||||
the microcontroller system to the debug system. <br>
|
||||
Only a 8 bit value is transmitted.
|
||||
</p>
|
||||
<pre>
|
||||
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
|
||||
{
|
||||
/* check if debugger connected and ITM channel enabled for tracing */
|
||||
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
|
||||
(ITM->TCR & ITM_TCR_ITMENA) &&
|
||||
(ITM->TER & (1UL << 0)) )
|
||||
{
|
||||
while (ITM->PORT[0].u32 == 0);
|
||||
ITM->PORT[0].u8 = (uint8_t)ch;
|
||||
}
|
||||
return (ch);
|
||||
}</pre>
|
||||
|
||||
<h3>ITM_ReceiveChar</h3>
|
||||
<p>
|
||||
ITM communication channel is only capable for OUT direction. For IN direction
|
||||
a globel variable is used. A simple mechansim detects if a character is received.
|
||||
The project to test need to be build with debug information.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
|
||||
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
|
||||
</p>
|
||||
<pre>
|
||||
extern volatile int ITM_RxBuffer; /* variable to receive characters */
|
||||
</pre>
|
||||
<p>
|
||||
A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
|
||||
or contains a valid value.
|
||||
</p>
|
||||
<pre>
|
||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
|
||||
</pre>
|
||||
<p>
|
||||
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
|
||||
It returns the received character or '-1' if no character was available.
|
||||
</p>
|
||||
<pre>
|
||||
static __INLINE int ITM_ReceiveChar (void) {
|
||||
int ch = -1; /* no character available */
|
||||
|
||||
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
|
||||
ch = ITM_RxBuffer;
|
||||
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
|
||||
}
|
||||
|
||||
return (ch);
|
||||
}
|
||||
</pre>
|
||||
|
||||
<h3>ITM_CheckChar</h3>
|
||||
<p>
|
||||
<strong>ITM_CheckChar</strong> is used to check if a character is received.
|
||||
</p>
|
||||
<pre>
|
||||
static __INLINE int ITM_CheckChar (void) {
|
||||
|
||||
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
|
||||
return (0); /* no character available */
|
||||
} else {
|
||||
return (1); /* character available */
|
||||
}
|
||||
}</pre>
|
||||
|
||||
|
||||
<h2>ITM Debug Support in uVision</h2>
|
||||
<p>
|
||||
uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
|
||||
display the debug data.
|
||||
</p>
|
||||
<p>Direction microcontroller system -> uVision:</p>
|
||||
<ul>
|
||||
<li>
|
||||
Characters received via ITM communication channel 0 are written in a printf style
|
||||
to <strong>Debug (printf) Viewer</strong> window.
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<p>Direction uVision -> microcontroller system:</p>
|
||||
<ul>
|
||||
<li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
|
||||
<li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
|
||||
<li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
|
||||
</ul>
|
||||
|
||||
<p class="Note">Note</p>
|
||||
<ul>
|
||||
<li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<h2>RTX Kernel awareness in uVision</h2>
|
||||
<p>
|
||||
uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
|
||||
No format overhead is necessary.<br>
|
||||
uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
|
||||
to ITM communication channel 31.
|
||||
</p>
|
||||
|
||||
<p>Following RTX events are traced:</p>
|
||||
<ul>
|
||||
<li>Task Create / Delete event
|
||||
<ol>
|
||||
<li>32 bit access. Task start address is transmitted</li>
|
||||
<li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
|
||||
High byte holds Create/Delete flag, Low byte holds TASK ID.
|
||||
</li>
|
||||
</ol>
|
||||
</li>
|
||||
<li>Task switch event
|
||||
<ol>
|
||||
<li>8 bit access. Task ID of current task is transmitted</li>
|
||||
</ol>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<p class="Note">Note</p>
|
||||
<ul>
|
||||
<li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<p class="MsoNormal"><span lang="EN-GB"> </span></p>
|
||||
|
||||
<hr>
|
||||
|
||||
<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
|
||||
All rights reserved.<br>
|
||||
Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
|
||||
</p>
|
||||
|
||||
</body>
|
||||
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -1,12 +1,12 @@
|
|||
History of updates to CMSISv1p30_LPC13xx
|
||||
========================================
|
||||
|
||||
18 February 2010
|
||||
----------------
|
||||
system_LPC13xx.c updated to new version (dated 18 February 2010),
|
||||
changing value of SYSPLLCTRL_Val from 0x05 to 0x25
|
||||
|
||||
23 March 2010
|
||||
-------------
|
||||
Optimisation level of release build of project changed from
|
||||
-O2 to -Os.
|
||||
History of updates to CMSISv1p30_LPC13xx
|
||||
========================================
|
||||
|
||||
18 February 2010
|
||||
----------------
|
||||
system_LPC13xx.c updated to new version (dated 18 February 2010),
|
||||
changing value of SYSPLLCTRL_Val from 0x05 to 0x25
|
||||
|
||||
23 March 2010
|
||||
-------------
|
||||
Optimisation level of release build of project changed from
|
||||
-O2 to -Os.
|
||||
|
|
|
|||
|
|
@ -1,493 +1,493 @@
|
|||
/**************************************************************************//**
|
||||
* @file LPC13xx.h
|
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
|
||||
* NXP LPC13xx Device Series
|
||||
* @version V1.01
|
||||
* @date 19. October 2009
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __LPC13xx_H__
|
||||
#define __LPC13xx_H__
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ---------- Interrupt Number Definition -----------------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** LPC13xx Specific Interrupt Numbers *******************************************************/
|
||||
WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
|
||||
WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */
|
||||
WAKEUP2_IRQn = 2,
|
||||
WAKEUP3_IRQn = 3,
|
||||
WAKEUP4_IRQn = 4,
|
||||
WAKEUP5_IRQn = 5,
|
||||
WAKEUP6_IRQn = 6,
|
||||
WAKEUP7_IRQn = 7,
|
||||
WAKEUP8_IRQn = 8,
|
||||
WAKEUP9_IRQn = 9,
|
||||
WAKEUP10_IRQn = 10,
|
||||
WAKEUP11_IRQn = 11,
|
||||
WAKEUP12_IRQn = 12,
|
||||
WAKEUP13_IRQn = 13,
|
||||
WAKEUP14_IRQn = 14,
|
||||
WAKEUP15_IRQn = 15,
|
||||
WAKEUP16_IRQn = 16,
|
||||
WAKEUP17_IRQn = 17,
|
||||
WAKEUP18_IRQn = 18,
|
||||
WAKEUP19_IRQn = 19,
|
||||
WAKEUP20_IRQn = 20,
|
||||
WAKEUP21_IRQn = 21,
|
||||
WAKEUP22_IRQn = 22,
|
||||
WAKEUP23_IRQn = 23,
|
||||
WAKEUP24_IRQn = 24,
|
||||
WAKEUP25_IRQn = 25,
|
||||
WAKEUP26_IRQn = 26,
|
||||
WAKEUP27_IRQn = 27,
|
||||
WAKEUP28_IRQn = 28,
|
||||
WAKEUP29_IRQn = 29,
|
||||
WAKEUP30_IRQn = 30,
|
||||
WAKEUP31_IRQn = 31,
|
||||
WAKEUP32_IRQn = 32,
|
||||
WAKEUP33_IRQn = 33,
|
||||
WAKEUP34_IRQn = 34,
|
||||
WAKEUP35_IRQn = 35,
|
||||
WAKEUP36_IRQn = 36,
|
||||
WAKEUP37_IRQn = 37,
|
||||
WAKEUP38_IRQn = 38,
|
||||
WAKEUP39_IRQn = 39,
|
||||
I2C_IRQn = 40, /*!< I2C Interrupt */
|
||||
TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */
|
||||
TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */
|
||||
TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */
|
||||
TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */
|
||||
SSP_IRQn = 45, /*!< SSP Interrupt */
|
||||
UART_IRQn = 46, /*!< UART Interrupt */
|
||||
USB_IRQn = 47, /*!< USB Regular Interrupt */
|
||||
USB_FIQn = 48, /*!< USB Fast Interrupt */
|
||||
ADC_IRQn = 49, /*!< A/D Converter Interrupt */
|
||||
WDT_IRQn = 50, /*!< Watchdog timer Interrupt */
|
||||
BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */
|
||||
EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */
|
||||
EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */
|
||||
EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */
|
||||
EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ----------- Processor and Core Peripheral Section ------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_LPC13xx.h" /* System Header */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Device Specific Peripheral registers structures */
|
||||
/******************************************************************************/
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/*------------- System Control (SYSCON) --------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */
|
||||
__IO uint32_t PRESETCTRL;
|
||||
__IO uint32_t SYSPLLCTRL; /* Sys PLL control */
|
||||
__IO uint32_t SYSPLLSTAT;
|
||||
__IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */
|
||||
__IO uint32_t USBPLLSTAT;
|
||||
uint32_t RESERVED0[2];
|
||||
|
||||
__IO uint32_t SYSOSCCTRL; /* Offset 0x20 */
|
||||
__IO uint32_t WDTOSCCTRL;
|
||||
__IO uint32_t IRCCTRL;
|
||||
uint32_t RESERVED1[1];
|
||||
__IO uint32_t SYSRESSTAT; /* Offset 0x30 */
|
||||
uint32_t RESERVED2[3];
|
||||
__IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */
|
||||
__IO uint32_t SYSPLLCLKUEN;
|
||||
__IO uint32_t USBPLLCLKSEL;
|
||||
__IO uint32_t USBPLLCLKUEN;
|
||||
uint32_t RESERVED3[8];
|
||||
|
||||
__IO uint32_t MAINCLKSEL; /* Offset 0x70 */
|
||||
__IO uint32_t MAINCLKUEN;
|
||||
__IO uint32_t SYSAHBCLKDIV;
|
||||
uint32_t RESERVED4[1];
|
||||
|
||||
__IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */
|
||||
uint32_t RESERVED5[4];
|
||||
__IO uint32_t SSPCLKDIV;
|
||||
__IO uint32_t UARTCLKDIV;
|
||||
uint32_t RESERVED6[4];
|
||||
__IO uint32_t TRACECLKDIV;
|
||||
|
||||
__IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */
|
||||
uint32_t RESERVED7[3];
|
||||
|
||||
__IO uint32_t USBCLKSEL; /* Offset 0xC0 */
|
||||
__IO uint32_t USBCLKUEN;
|
||||
__IO uint32_t USBCLKDIV;
|
||||
uint32_t RESERVED8[1];
|
||||
__IO uint32_t WDTCLKSEL; /* Offset 0xD0 */
|
||||
__IO uint32_t WDTCLKUEN;
|
||||
__IO uint32_t WDTCLKDIV;
|
||||
uint32_t RESERVED9[1];
|
||||
__IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */
|
||||
__IO uint32_t CLKOUTUEN;
|
||||
__IO uint32_t CLKOUTDIV;
|
||||
uint32_t RESERVED10[5];
|
||||
|
||||
__IO uint32_t PIOPORCAP0; /* Offset 0x100 */
|
||||
__IO uint32_t PIOPORCAP1;
|
||||
uint32_t RESERVED11[18];
|
||||
|
||||
__IO uint32_t BODCTRL; /* Offset 0x150 */
|
||||
uint32_t RESERVED12[1];
|
||||
__IO uint32_t SYSTCKCAL;
|
||||
uint32_t RESERVED13[41];
|
||||
|
||||
__IO uint32_t STARTAPRP0; /* Offset 0x200 */
|
||||
__IO uint32_t STARTERP0;
|
||||
__IO uint32_t STARTRSRP0CLR;
|
||||
__IO uint32_t STARTSRP0;
|
||||
__IO uint32_t STARTAPRP1;
|
||||
__IO uint32_t STARTERP1;
|
||||
__IO uint32_t STARTRSRP1CLR;
|
||||
__IO uint32_t STARTSRP1;
|
||||
uint32_t RESERVED14[4];
|
||||
|
||||
__IO uint32_t PDSLEEPCFG; /* Offset 0x230 */
|
||||
__IO uint32_t PDAWAKECFG;
|
||||
__IO uint32_t PDRUNCFG;
|
||||
uint32_t RESERVED15[110];
|
||||
__I uint32_t DEVICE_ID;
|
||||
} LPC_SYSCON_TypeDef;
|
||||
|
||||
|
||||
/*------------- Pin Connect Block (IOCON) --------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PIO2_6;
|
||||
uint32_t RESERVED0[1];
|
||||
__IO uint32_t PIO2_0;
|
||||
__IO uint32_t RESET_PIO0_0;
|
||||
__IO uint32_t PIO0_1;
|
||||
__IO uint32_t PIO1_8;
|
||||
uint32_t RESERVED1[1];
|
||||
__IO uint32_t PIO0_2;
|
||||
|
||||
__IO uint32_t PIO2_7;
|
||||
__IO uint32_t PIO2_8;
|
||||
__IO uint32_t PIO2_1;
|
||||
__IO uint32_t PIO0_3;
|
||||
__IO uint32_t PIO0_4;
|
||||
__IO uint32_t PIO0_5;
|
||||
__IO uint32_t PIO1_9;
|
||||
__IO uint32_t PIO3_4;
|
||||
|
||||
__IO uint32_t PIO2_4;
|
||||
__IO uint32_t PIO2_5;
|
||||
__IO uint32_t PIO3_5;
|
||||
__IO uint32_t PIO0_6;
|
||||
__IO uint32_t PIO0_7;
|
||||
__IO uint32_t PIO2_9;
|
||||
__IO uint32_t PIO2_10;
|
||||
__IO uint32_t PIO2_2;
|
||||
|
||||
__IO uint32_t PIO0_8;
|
||||
__IO uint32_t PIO0_9;
|
||||
__IO uint32_t JTAG_TCK_PIO0_10;
|
||||
__IO uint32_t PIO1_10;
|
||||
__IO uint32_t PIO2_11;
|
||||
__IO uint32_t JTAG_TDI_PIO0_11;
|
||||
__IO uint32_t JTAG_TMS_PIO1_0;
|
||||
__IO uint32_t JTAG_TDO_PIO1_1;
|
||||
|
||||
__IO uint32_t JTAG_nTRST_PIO1_2;
|
||||
__IO uint32_t PIO3_0;
|
||||
__IO uint32_t PIO3_1;
|
||||
__IO uint32_t PIO2_3;
|
||||
__IO uint32_t ARM_SWDIO_PIO1_3;
|
||||
__IO uint32_t PIO1_4;
|
||||
__IO uint32_t PIO1_11;
|
||||
__IO uint32_t PIO3_2;
|
||||
|
||||
__IO uint32_t PIO1_5;
|
||||
__IO uint32_t PIO1_6;
|
||||
__IO uint32_t PIO1_7;
|
||||
__IO uint32_t PIO3_3;
|
||||
__IO uint32_t SCKLOC; /* For HB1 only, new feature */
|
||||
} LPC_IOCON_TypeDef;
|
||||
|
||||
|
||||
/*------------- Power Management Unit (PMU) --------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PCON;
|
||||
__IO uint32_t GPREG0;
|
||||
__IO uint32_t GPREG1;
|
||||
__IO uint32_t GPREG2;
|
||||
__IO uint32_t GPREG3;
|
||||
__IO uint32_t GPREG4;
|
||||
} LPC_PMU_TypeDef;
|
||||
|
||||
|
||||
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
__IO uint32_t MASKED_ACCESS[4096];
|
||||
struct {
|
||||
uint32_t RESERVED0[4095];
|
||||
__IO uint32_t DATA;
|
||||
};
|
||||
};
|
||||
uint32_t RESERVED1[4096];
|
||||
__IO uint32_t DIR;
|
||||
__IO uint32_t IS;
|
||||
__IO uint32_t IBE;
|
||||
__IO uint32_t IEV;
|
||||
__IO uint32_t IE;
|
||||
__IO uint32_t RIS;
|
||||
__IO uint32_t MIS;
|
||||
__IO uint32_t IC;
|
||||
} LPC_GPIO_TypeDef;
|
||||
|
||||
|
||||
/*------------- Timer (TMR) --------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IR;
|
||||
__IO uint32_t TCR;
|
||||
__IO uint32_t TC;
|
||||
__IO uint32_t PR;
|
||||
__IO uint32_t PC;
|
||||
__IO uint32_t MCR;
|
||||
__IO uint32_t MR0;
|
||||
__IO uint32_t MR1;
|
||||
__IO uint32_t MR2;
|
||||
__IO uint32_t MR3;
|
||||
__IO uint32_t CCR;
|
||||
__I uint32_t CR0;
|
||||
uint32_t RESERVED1[3];
|
||||
__IO uint32_t EMR;
|
||||
uint32_t RESERVED2[12];
|
||||
__IO uint32_t CTCR;
|
||||
__IO uint32_t PWMC;
|
||||
} LPC_TMR_TypeDef;
|
||||
|
||||
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
__I uint32_t RBR;
|
||||
__O uint32_t THR;
|
||||
__IO uint32_t DLL;
|
||||
};
|
||||
union {
|
||||
__IO uint32_t DLM;
|
||||
__IO uint32_t IER;
|
||||
};
|
||||
union {
|
||||
__I uint32_t IIR;
|
||||
__O uint32_t FCR;
|
||||
};
|
||||
__IO uint32_t LCR;
|
||||
__IO uint32_t MCR;
|
||||
__I uint32_t LSR;
|
||||
__I uint32_t MSR;
|
||||
__IO uint32_t SCR;
|
||||
__IO uint32_t ACR;
|
||||
__IO uint32_t ICR;
|
||||
__IO uint32_t FDR;
|
||||
uint32_t RESERVED0;
|
||||
__IO uint32_t TER;
|
||||
uint32_t RESERVED1[6];
|
||||
__IO uint32_t RS485CTRL;
|
||||
__IO uint32_t ADRMATCH;
|
||||
__IO uint32_t RS485DLY;
|
||||
__I uint32_t FIFOLVL;
|
||||
} LPC_UART_TypeDef;
|
||||
|
||||
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR0;
|
||||
__IO uint32_t CR1;
|
||||
__IO uint32_t DR;
|
||||
__I uint32_t SR;
|
||||
__IO uint32_t CPSR;
|
||||
__IO uint32_t IMSC;
|
||||
__IO uint32_t RIS;
|
||||
__IO uint32_t MIS;
|
||||
__IO uint32_t ICR;
|
||||
} LPC_SSP_TypeDef;
|
||||
|
||||
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CONSET;
|
||||
__I uint32_t STAT;
|
||||
__IO uint32_t DAT;
|
||||
__IO uint32_t ADR0;
|
||||
__IO uint32_t SCLH;
|
||||
__IO uint32_t SCLL;
|
||||
__O uint32_t CONCLR;
|
||||
__IO uint32_t MMCTRL;
|
||||
__IO uint32_t ADR1;
|
||||
__IO uint32_t ADR2;
|
||||
__IO uint32_t ADR3;
|
||||
__I uint32_t DATA_BUFFER;
|
||||
__IO uint32_t MASK0;
|
||||
__IO uint32_t MASK1;
|
||||
__IO uint32_t MASK2;
|
||||
__IO uint32_t MASK3;
|
||||
} LPC_I2C_TypeDef;
|
||||
|
||||
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t MOD;
|
||||
__IO uint32_t TC;
|
||||
__O uint32_t FEED;
|
||||
__I uint32_t TV;
|
||||
} LPC_WDT_TypeDef;
|
||||
|
||||
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR;
|
||||
__IO uint32_t GDR;
|
||||
uint32_t RESERVED0;
|
||||
__IO uint32_t INTEN;
|
||||
__I uint32_t DR0;
|
||||
__I uint32_t DR1;
|
||||
__I uint32_t DR2;
|
||||
__I uint32_t DR3;
|
||||
__I uint32_t DR4;
|
||||
__I uint32_t DR5;
|
||||
__I uint32_t DR6;
|
||||
__I uint32_t DR7;
|
||||
__I uint32_t STAT;
|
||||
} LPC_ADC_TypeDef;
|
||||
|
||||
|
||||
/*------------- Universal Serial Bus (USB) -----------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t DevIntSt; /* USB Device Interrupt Registers */
|
||||
__IO uint32_t DevIntEn;
|
||||
__O uint32_t DevIntClr;
|
||||
__O uint32_t DevIntSet;
|
||||
|
||||
__O uint32_t CmdCode; /* USB Device SIE Command Registers */
|
||||
__I uint32_t CmdData;
|
||||
|
||||
__I uint32_t RxData; /* USB Device Transfer Registers */
|
||||
__O uint32_t TxData;
|
||||
__I uint32_t RxPLen;
|
||||
__O uint32_t TxPLen;
|
||||
__IO uint32_t Ctrl;
|
||||
__O uint32_t DevFIQSel;
|
||||
} LPC_USB_TypeDef;
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
/* Base addresses */
|
||||
#define LPC_FLASH_BASE (0x00000000UL)
|
||||
#define LPC_RAM_BASE (0x10000000UL)
|
||||
#define LPC_APB0_BASE (0x40000000UL)
|
||||
#define LPC_AHB_BASE (0x50000000UL)
|
||||
|
||||
/* APB0 peripherals */
|
||||
#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
|
||||
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
|
||||
#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
|
||||
#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
|
||||
#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
|
||||
#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
|
||||
#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
|
||||
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
|
||||
#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000)
|
||||
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
|
||||
#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000)
|
||||
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
|
||||
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
|
||||
|
||||
/* AHB peripherals */
|
||||
#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
|
||||
#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
|
||||
#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
|
||||
#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
|
||||
#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
|
||||
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
|
||||
#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
|
||||
#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
|
||||
#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
|
||||
#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
|
||||
#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
|
||||
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
|
||||
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
|
||||
#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE )
|
||||
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
|
||||
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
|
||||
#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
|
||||
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
|
||||
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
|
||||
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
|
||||
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
|
||||
|
||||
#endif // __LPC13xx_H__
|
||||
/**************************************************************************//**
|
||||
* @file LPC13xx.h
|
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
|
||||
* NXP LPC13xx Device Series
|
||||
* @version V1.01
|
||||
* @date 19. October 2009
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __LPC13xx_H__
|
||||
#define __LPC13xx_H__
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ---------- Interrupt Number Definition -----------------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** LPC13xx Specific Interrupt Numbers *******************************************************/
|
||||
WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
|
||||
WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */
|
||||
WAKEUP2_IRQn = 2,
|
||||
WAKEUP3_IRQn = 3,
|
||||
WAKEUP4_IRQn = 4,
|
||||
WAKEUP5_IRQn = 5,
|
||||
WAKEUP6_IRQn = 6,
|
||||
WAKEUP7_IRQn = 7,
|
||||
WAKEUP8_IRQn = 8,
|
||||
WAKEUP9_IRQn = 9,
|
||||
WAKEUP10_IRQn = 10,
|
||||
WAKEUP11_IRQn = 11,
|
||||
WAKEUP12_IRQn = 12,
|
||||
WAKEUP13_IRQn = 13,
|
||||
WAKEUP14_IRQn = 14,
|
||||
WAKEUP15_IRQn = 15,
|
||||
WAKEUP16_IRQn = 16,
|
||||
WAKEUP17_IRQn = 17,
|
||||
WAKEUP18_IRQn = 18,
|
||||
WAKEUP19_IRQn = 19,
|
||||
WAKEUP20_IRQn = 20,
|
||||
WAKEUP21_IRQn = 21,
|
||||
WAKEUP22_IRQn = 22,
|
||||
WAKEUP23_IRQn = 23,
|
||||
WAKEUP24_IRQn = 24,
|
||||
WAKEUP25_IRQn = 25,
|
||||
WAKEUP26_IRQn = 26,
|
||||
WAKEUP27_IRQn = 27,
|
||||
WAKEUP28_IRQn = 28,
|
||||
WAKEUP29_IRQn = 29,
|
||||
WAKEUP30_IRQn = 30,
|
||||
WAKEUP31_IRQn = 31,
|
||||
WAKEUP32_IRQn = 32,
|
||||
WAKEUP33_IRQn = 33,
|
||||
WAKEUP34_IRQn = 34,
|
||||
WAKEUP35_IRQn = 35,
|
||||
WAKEUP36_IRQn = 36,
|
||||
WAKEUP37_IRQn = 37,
|
||||
WAKEUP38_IRQn = 38,
|
||||
WAKEUP39_IRQn = 39,
|
||||
I2C_IRQn = 40, /*!< I2C Interrupt */
|
||||
TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */
|
||||
TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */
|
||||
TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */
|
||||
TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */
|
||||
SSP_IRQn = 45, /*!< SSP Interrupt */
|
||||
UART_IRQn = 46, /*!< UART Interrupt */
|
||||
USB_IRQn = 47, /*!< USB Regular Interrupt */
|
||||
USB_FIQn = 48, /*!< USB Fast Interrupt */
|
||||
ADC_IRQn = 49, /*!< A/D Converter Interrupt */
|
||||
WDT_IRQn = 50, /*!< Watchdog timer Interrupt */
|
||||
BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */
|
||||
EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */
|
||||
EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */
|
||||
EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */
|
||||
EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ----------- Processor and Core Peripheral Section ------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_LPC13xx.h" /* System Header */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Device Specific Peripheral registers structures */
|
||||
/******************************************************************************/
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/*------------- System Control (SYSCON) --------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */
|
||||
__IO uint32_t PRESETCTRL;
|
||||
__IO uint32_t SYSPLLCTRL; /* Sys PLL control */
|
||||
__IO uint32_t SYSPLLSTAT;
|
||||
__IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */
|
||||
__IO uint32_t USBPLLSTAT;
|
||||
uint32_t RESERVED0[2];
|
||||
|
||||
__IO uint32_t SYSOSCCTRL; /* Offset 0x20 */
|
||||
__IO uint32_t WDTOSCCTRL;
|
||||
__IO uint32_t IRCCTRL;
|
||||
uint32_t RESERVED1[1];
|
||||
__IO uint32_t SYSRESSTAT; /* Offset 0x30 */
|
||||
uint32_t RESERVED2[3];
|
||||
__IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */
|
||||
__IO uint32_t SYSPLLCLKUEN;
|
||||
__IO uint32_t USBPLLCLKSEL;
|
||||
__IO uint32_t USBPLLCLKUEN;
|
||||
uint32_t RESERVED3[8];
|
||||
|
||||
__IO uint32_t MAINCLKSEL; /* Offset 0x70 */
|
||||
__IO uint32_t MAINCLKUEN;
|
||||
__IO uint32_t SYSAHBCLKDIV;
|
||||
uint32_t RESERVED4[1];
|
||||
|
||||
__IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */
|
||||
uint32_t RESERVED5[4];
|
||||
__IO uint32_t SSPCLKDIV;
|
||||
__IO uint32_t UARTCLKDIV;
|
||||
uint32_t RESERVED6[4];
|
||||
__IO uint32_t TRACECLKDIV;
|
||||
|
||||
__IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */
|
||||
uint32_t RESERVED7[3];
|
||||
|
||||
__IO uint32_t USBCLKSEL; /* Offset 0xC0 */
|
||||
__IO uint32_t USBCLKUEN;
|
||||
__IO uint32_t USBCLKDIV;
|
||||
uint32_t RESERVED8[1];
|
||||
__IO uint32_t WDTCLKSEL; /* Offset 0xD0 */
|
||||
__IO uint32_t WDTCLKUEN;
|
||||
__IO uint32_t WDTCLKDIV;
|
||||
uint32_t RESERVED9[1];
|
||||
__IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */
|
||||
__IO uint32_t CLKOUTUEN;
|
||||
__IO uint32_t CLKOUTDIV;
|
||||
uint32_t RESERVED10[5];
|
||||
|
||||
__IO uint32_t PIOPORCAP0; /* Offset 0x100 */
|
||||
__IO uint32_t PIOPORCAP1;
|
||||
uint32_t RESERVED11[18];
|
||||
|
||||
__IO uint32_t BODCTRL; /* Offset 0x150 */
|
||||
uint32_t RESERVED12[1];
|
||||
__IO uint32_t SYSTCKCAL;
|
||||
uint32_t RESERVED13[41];
|
||||
|
||||
__IO uint32_t STARTAPRP0; /* Offset 0x200 */
|
||||
__IO uint32_t STARTERP0;
|
||||
__IO uint32_t STARTRSRP0CLR;
|
||||
__IO uint32_t STARTSRP0;
|
||||
__IO uint32_t STARTAPRP1;
|
||||
__IO uint32_t STARTERP1;
|
||||
__IO uint32_t STARTRSRP1CLR;
|
||||
__IO uint32_t STARTSRP1;
|
||||
uint32_t RESERVED14[4];
|
||||
|
||||
__IO uint32_t PDSLEEPCFG; /* Offset 0x230 */
|
||||
__IO uint32_t PDAWAKECFG;
|
||||
__IO uint32_t PDRUNCFG;
|
||||
uint32_t RESERVED15[110];
|
||||
__I uint32_t DEVICE_ID;
|
||||
} LPC_SYSCON_TypeDef;
|
||||
|
||||
|
||||
/*------------- Pin Connect Block (IOCON) --------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PIO2_6;
|
||||
uint32_t RESERVED0[1];
|
||||
__IO uint32_t PIO2_0;
|
||||
__IO uint32_t RESET_PIO0_0;
|
||||
__IO uint32_t PIO0_1;
|
||||
__IO uint32_t PIO1_8;
|
||||
uint32_t RESERVED1[1];
|
||||
__IO uint32_t PIO0_2;
|
||||
|
||||
__IO uint32_t PIO2_7;
|
||||
__IO uint32_t PIO2_8;
|
||||
__IO uint32_t PIO2_1;
|
||||
__IO uint32_t PIO0_3;
|
||||
__IO uint32_t PIO0_4;
|
||||
__IO uint32_t PIO0_5;
|
||||
__IO uint32_t PIO1_9;
|
||||
__IO uint32_t PIO3_4;
|
||||
|
||||
__IO uint32_t PIO2_4;
|
||||
__IO uint32_t PIO2_5;
|
||||
__IO uint32_t PIO3_5;
|
||||
__IO uint32_t PIO0_6;
|
||||
__IO uint32_t PIO0_7;
|
||||
__IO uint32_t PIO2_9;
|
||||
__IO uint32_t PIO2_10;
|
||||
__IO uint32_t PIO2_2;
|
||||
|
||||
__IO uint32_t PIO0_8;
|
||||
__IO uint32_t PIO0_9;
|
||||
__IO uint32_t JTAG_TCK_PIO0_10;
|
||||
__IO uint32_t PIO1_10;
|
||||
__IO uint32_t PIO2_11;
|
||||
__IO uint32_t JTAG_TDI_PIO0_11;
|
||||
__IO uint32_t JTAG_TMS_PIO1_0;
|
||||
__IO uint32_t JTAG_TDO_PIO1_1;
|
||||
|
||||
__IO uint32_t JTAG_nTRST_PIO1_2;
|
||||
__IO uint32_t PIO3_0;
|
||||
__IO uint32_t PIO3_1;
|
||||
__IO uint32_t PIO2_3;
|
||||
__IO uint32_t ARM_SWDIO_PIO1_3;
|
||||
__IO uint32_t PIO1_4;
|
||||
__IO uint32_t PIO1_11;
|
||||
__IO uint32_t PIO3_2;
|
||||
|
||||
__IO uint32_t PIO1_5;
|
||||
__IO uint32_t PIO1_6;
|
||||
__IO uint32_t PIO1_7;
|
||||
__IO uint32_t PIO3_3;
|
||||
__IO uint32_t SCKLOC; /* For HB1 only, new feature */
|
||||
} LPC_IOCON_TypeDef;
|
||||
|
||||
|
||||
/*------------- Power Management Unit (PMU) --------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PCON;
|
||||
__IO uint32_t GPREG0;
|
||||
__IO uint32_t GPREG1;
|
||||
__IO uint32_t GPREG2;
|
||||
__IO uint32_t GPREG3;
|
||||
__IO uint32_t GPREG4;
|
||||
} LPC_PMU_TypeDef;
|
||||
|
||||
|
||||
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
__IO uint32_t MASKED_ACCESS[4096];
|
||||
struct {
|
||||
uint32_t RESERVED0[4095];
|
||||
__IO uint32_t DATA;
|
||||
};
|
||||
};
|
||||
uint32_t RESERVED1[4096];
|
||||
__IO uint32_t DIR;
|
||||
__IO uint32_t IS;
|
||||
__IO uint32_t IBE;
|
||||
__IO uint32_t IEV;
|
||||
__IO uint32_t IE;
|
||||
__IO uint32_t RIS;
|
||||
__IO uint32_t MIS;
|
||||
__IO uint32_t IC;
|
||||
} LPC_GPIO_TypeDef;
|
||||
|
||||
|
||||
/*------------- Timer (TMR) --------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IR;
|
||||
__IO uint32_t TCR;
|
||||
__IO uint32_t TC;
|
||||
__IO uint32_t PR;
|
||||
__IO uint32_t PC;
|
||||
__IO uint32_t MCR;
|
||||
__IO uint32_t MR0;
|
||||
__IO uint32_t MR1;
|
||||
__IO uint32_t MR2;
|
||||
__IO uint32_t MR3;
|
||||
__IO uint32_t CCR;
|
||||
__I uint32_t CR0;
|
||||
uint32_t RESERVED1[3];
|
||||
__IO uint32_t EMR;
|
||||
uint32_t RESERVED2[12];
|
||||
__IO uint32_t CTCR;
|
||||
__IO uint32_t PWMC;
|
||||
} LPC_TMR_TypeDef;
|
||||
|
||||
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
__I uint32_t RBR;
|
||||
__O uint32_t THR;
|
||||
__IO uint32_t DLL;
|
||||
};
|
||||
union {
|
||||
__IO uint32_t DLM;
|
||||
__IO uint32_t IER;
|
||||
};
|
||||
union {
|
||||
__I uint32_t IIR;
|
||||
__O uint32_t FCR;
|
||||
};
|
||||
__IO uint32_t LCR;
|
||||
__IO uint32_t MCR;
|
||||
__I uint32_t LSR;
|
||||
__I uint32_t MSR;
|
||||
__IO uint32_t SCR;
|
||||
__IO uint32_t ACR;
|
||||
__IO uint32_t ICR;
|
||||
__IO uint32_t FDR;
|
||||
uint32_t RESERVED0;
|
||||
__IO uint32_t TER;
|
||||
uint32_t RESERVED1[6];
|
||||
__IO uint32_t RS485CTRL;
|
||||
__IO uint32_t ADRMATCH;
|
||||
__IO uint32_t RS485DLY;
|
||||
__I uint32_t FIFOLVL;
|
||||
} LPC_UART_TypeDef;
|
||||
|
||||
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR0;
|
||||
__IO uint32_t CR1;
|
||||
__IO uint32_t DR;
|
||||
__I uint32_t SR;
|
||||
__IO uint32_t CPSR;
|
||||
__IO uint32_t IMSC;
|
||||
__IO uint32_t RIS;
|
||||
__IO uint32_t MIS;
|
||||
__IO uint32_t ICR;
|
||||
} LPC_SSP_TypeDef;
|
||||
|
||||
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CONSET;
|
||||
__I uint32_t STAT;
|
||||
__IO uint32_t DAT;
|
||||
__IO uint32_t ADR0;
|
||||
__IO uint32_t SCLH;
|
||||
__IO uint32_t SCLL;
|
||||
__O uint32_t CONCLR;
|
||||
__IO uint32_t MMCTRL;
|
||||
__IO uint32_t ADR1;
|
||||
__IO uint32_t ADR2;
|
||||
__IO uint32_t ADR3;
|
||||
__I uint32_t DATA_BUFFER;
|
||||
__IO uint32_t MASK0;
|
||||
__IO uint32_t MASK1;
|
||||
__IO uint32_t MASK2;
|
||||
__IO uint32_t MASK3;
|
||||
} LPC_I2C_TypeDef;
|
||||
|
||||
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t MOD;
|
||||
__IO uint32_t TC;
|
||||
__O uint32_t FEED;
|
||||
__I uint32_t TV;
|
||||
} LPC_WDT_TypeDef;
|
||||
|
||||
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR;
|
||||
__IO uint32_t GDR;
|
||||
uint32_t RESERVED0;
|
||||
__IO uint32_t INTEN;
|
||||
__I uint32_t DR0;
|
||||
__I uint32_t DR1;
|
||||
__I uint32_t DR2;
|
||||
__I uint32_t DR3;
|
||||
__I uint32_t DR4;
|
||||
__I uint32_t DR5;
|
||||
__I uint32_t DR6;
|
||||
__I uint32_t DR7;
|
||||
__I uint32_t STAT;
|
||||
} LPC_ADC_TypeDef;
|
||||
|
||||
|
||||
/*------------- Universal Serial Bus (USB) -----------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t DevIntSt; /* USB Device Interrupt Registers */
|
||||
__IO uint32_t DevIntEn;
|
||||
__O uint32_t DevIntClr;
|
||||
__O uint32_t DevIntSet;
|
||||
|
||||
__O uint32_t CmdCode; /* USB Device SIE Command Registers */
|
||||
__I uint32_t CmdData;
|
||||
|
||||
__I uint32_t RxData; /* USB Device Transfer Registers */
|
||||
__O uint32_t TxData;
|
||||
__I uint32_t RxPLen;
|
||||
__O uint32_t TxPLen;
|
||||
__IO uint32_t Ctrl;
|
||||
__O uint32_t DevFIQSel;
|
||||
} LPC_USB_TypeDef;
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
/* Base addresses */
|
||||
#define LPC_FLASH_BASE (0x00000000UL)
|
||||
#define LPC_RAM_BASE (0x10000000UL)
|
||||
#define LPC_APB0_BASE (0x40000000UL)
|
||||
#define LPC_AHB_BASE (0x50000000UL)
|
||||
|
||||
/* APB0 peripherals */
|
||||
#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
|
||||
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
|
||||
#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
|
||||
#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
|
||||
#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
|
||||
#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
|
||||
#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
|
||||
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
|
||||
#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000)
|
||||
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
|
||||
#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000)
|
||||
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
|
||||
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
|
||||
|
||||
/* AHB peripherals */
|
||||
#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
|
||||
#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
|
||||
#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
|
||||
#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
|
||||
#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
|
||||
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
|
||||
#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
|
||||
#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
|
||||
#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
|
||||
#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
|
||||
#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
|
||||
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
|
||||
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
|
||||
#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE )
|
||||
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
|
||||
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
|
||||
#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
|
||||
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
|
||||
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
|
||||
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
|
||||
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
|
||||
|
||||
#endif // __LPC13xx_H__
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,64 +1,64 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_LPC13xx.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.01
|
||||
* @date 19. October 2009
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC13xx_H
|
||||
#define __SYSTEM_LPC13xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC13x_H */
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC13xx.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.01
|
||||
* @date 19. October 2009
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC13xx_H
|
||||
#define __SYSTEM_LPC13xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC13x_H */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,487 +1,487 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_LPC13xx.c
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.02
|
||||
* @date 18. February 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
// ******** Code Red **************
|
||||
// * Changed USBCLK_SETUP to 1
|
||||
// * Changed SYSPLLCTRL_Val to 0x25
|
||||
// ********************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC13xx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <e1> System Clock Setup
|
||||
// <e2> System Oscillator Enable
|
||||
// <o3.1> Select System Oscillator Frequency Range
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </e2>
|
||||
// <e4> Watchdog Oscillator Enable
|
||||
// <o5.0..4> Select Divider for Fclkana
|
||||
// <0=> 2 <1=> 4 <2=> 6 <3=> 8
|
||||
// <4=> 10 <5=> 12 <6=> 14 <7=> 16
|
||||
// <8=> 18 <9=> 20 <10=> 22 <11=> 24
|
||||
// <12=> 26 <13=> 28 <14=> 30 <15=> 32
|
||||
// <16=> 34 <17=> 36 <18=> 38 <19=> 40
|
||||
// <20=> 42 <21=> 44 <22=> 46 <23=> 48
|
||||
// <24=> 50 <25=> 52 <26=> 54 <27=> 56
|
||||
// <28=> 58 <29=> 60 <30=> 62 <31=> 64
|
||||
// <o5.5..8> Select Watchdog Oscillator Analog Frequency (Fclkana)
|
||||
// <0=> Disabled
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </e4>
|
||||
// <o6> Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> Invalid
|
||||
// <e7> Use System PLL
|
||||
// <i> F_pll = M * F_in
|
||||
// <i> F_in must be in the range of 10 MHz to 25 MHz
|
||||
// <o8.0..4> M: PLL Multiplier Selection
|
||||
// <1-32><#-1>
|
||||
// <o8.5..6> P: PLL Divider Selection
|
||||
// <0=> 2
|
||||
// <1=> 4
|
||||
// <2=> 8
|
||||
// <3=> 16
|
||||
// <o8.7> DIRECT: Direct CCO Clock Output Enable
|
||||
// <o8.8> BYPASS: PLL Bypass Enable
|
||||
// </e7>
|
||||
// <o9> Select Input Clock for Main clock (Register: MAINCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </e1>
|
||||
// <e10> USB Clock Setup
|
||||
// <e11> Use USB PLL
|
||||
// <i> F_pll = M * F_in
|
||||
// <i> F_in must be in the range of 10 MHz to 25 MHz
|
||||
// <o12.0..1> Select Input Clock for usb_pllclkin (Register: USBPLLCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <o13.0..4> M: PLL Multiplier Selection
|
||||
// <1-32><#-1>
|
||||
// <o13.5..6> P: PLL Divider Selection
|
||||
// <0=> 2
|
||||
// <1=> 4
|
||||
// <2=> 8
|
||||
// <3=> 16
|
||||
// <o13.7> DIRECT: Direct CCO Clock Output Enable
|
||||
// <o13.8> BYPASS: PLL Bypass Enable
|
||||
// </e11>
|
||||
// </e10>
|
||||
// <o14.0..7> System AHB Divider <0-255>
|
||||
// <i> 0 = is disabled
|
||||
// <o15.0> SYS Clock Enable
|
||||
// <o15.1> ROM Clock Enable
|
||||
// <o15.2> RAM Clock Enable
|
||||
// <o15.3> FLASH1 Clock Enable
|
||||
// <o15.4> FLASH2 Clock Enable
|
||||
// <o15.5> I2C Clock Enable
|
||||
// <o15.6> GPIO Clock Enable
|
||||
// <o15.7> CT16B0 Clock Enable
|
||||
// <o15.8> CT16B1 Clock Enable
|
||||
// <o15.9> CT32B0 Clock Enable
|
||||
// <o15.10> CT32B1 Clock Enable
|
||||
// <o15.11> SSP Clock Enable
|
||||
// <o15.12> UART Clock Enable
|
||||
// <o15.13> ADC Clock Enable
|
||||
// <o15.14> USB_REG Clock Enable
|
||||
// <o15.15> SWDT Clock Enable
|
||||
// <o15.16> IOCON Clock Enable
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSCLK_SETUP 1
|
||||
#define SYSOSC_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000
|
||||
#define WDTOSC_SETUP 0
|
||||
#define WDTOSCCTRL_Val 0x000000A0
|
||||
#define SYSPLLCLKSEL_Val 0x00000001
|
||||
#define SYSPLL_SETUP 1
|
||||
#define SYSPLLCTRL_Val 0x00000025
|
||||
#define MAINCLKSEL_Val 0x00000003
|
||||
|
||||
// ******** Code Red *********
|
||||
// * Changed USBCLK_SETUP to 1
|
||||
// ***************************
|
||||
#define USBCLK_SETUP 1
|
||||
#define USBPLL_SETUP 1
|
||||
#define USBPLLCLKSEL_Val 0x00000001
|
||||
#define USBPLLCTRL_Val 0x00000003
|
||||
#define SYSAHBCLKDIV_Val 0x00000001
|
||||
#define AHBCLKCTRL_Val 0x0001005F
|
||||
|
||||
/*--------------------- Memory Mapping Configuration -------------------------
|
||||
//
|
||||
// <e> Memory Mapping
|
||||
// <o1.0..1> System Memory Remap (Register: SYSMEMREMAP)
|
||||
// <0=> Bootloader mapped to address 0
|
||||
// <1=> RAM mapped to address 0
|
||||
// <2=> Flash mapped to address 0
|
||||
// <3=> Flash mapped to address 0
|
||||
// </e>
|
||||
*/
|
||||
#define MEMMAP_SETUP 0
|
||||
#define SYSMEMREMAP_Val 0x00000001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLUEN_Val), ~0x00000001))
|
||||
#error "USBPLLUEN: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF))
|
||||
#error "AHBCLKCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003))
|
||||
#error "SYSMEMREMAP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (SYSCLK_SETUP) /* System Clock Setup */
|
||||
#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
#else
|
||||
#define __WDT_OSC_CLK (1600000 / 2)
|
||||
#endif // WDTOSC_SETUP
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 2)
|
||||
#define __SYS_PLLCLKIN (__WDT_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#if (SYSPLL_SETUP) /* System PLL Setup */
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
#else
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1))
|
||||
#endif // SYSPLL_SETUP
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else // SYSCLK_SETUP
|
||||
#if (SYSAHBCLKDIV_Val == 0)
|
||||
#define __SYSTEM_CLOCK (0)
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__XTAL / SYSAHBCLKDIV_Val)
|
||||
#endif
|
||||
#endif // SYSCLK_SETUP
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__XTAL)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 400000; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = wdt_osc;
|
||||
} else {
|
||||
SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (SYSCLK_SETUP) /* System Clock Setup */
|
||||
#if (SYSOSC_SETUP) /* System Oscillator Setup */
|
||||
uint32_t i;
|
||||
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
#if (SYSPLL_SETUP) /* System PLL Setup */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
#endif
|
||||
#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
#endif
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
#endif
|
||||
|
||||
#if (USBCLK_SETUP) /* USB Clock Setup */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
#if (USBPLL_SETUP) /* USB PLL Setup */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
|
||||
#else
|
||||
LPC_SYSCON->USBCLKSEL = 0x01; /* Select Main Clock */
|
||||
#endif
|
||||
#else
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
|
||||
#endif
|
||||
|
||||
|
||||
#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */
|
||||
LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val;
|
||||
#endif
|
||||
}
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC13xx.c
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.02
|
||||
* @date 18. February 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
// ******** Code Red **************
|
||||
// * Changed USBCLK_SETUP to 1
|
||||
// * Changed SYSPLLCTRL_Val to 0x25
|
||||
// ********************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC13xx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <e1> System Clock Setup
|
||||
// <e2> System Oscillator Enable
|
||||
// <o3.1> Select System Oscillator Frequency Range
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </e2>
|
||||
// <e4> Watchdog Oscillator Enable
|
||||
// <o5.0..4> Select Divider for Fclkana
|
||||
// <0=> 2 <1=> 4 <2=> 6 <3=> 8
|
||||
// <4=> 10 <5=> 12 <6=> 14 <7=> 16
|
||||
// <8=> 18 <9=> 20 <10=> 22 <11=> 24
|
||||
// <12=> 26 <13=> 28 <14=> 30 <15=> 32
|
||||
// <16=> 34 <17=> 36 <18=> 38 <19=> 40
|
||||
// <20=> 42 <21=> 44 <22=> 46 <23=> 48
|
||||
// <24=> 50 <25=> 52 <26=> 54 <27=> 56
|
||||
// <28=> 58 <29=> 60 <30=> 62 <31=> 64
|
||||
// <o5.5..8> Select Watchdog Oscillator Analog Frequency (Fclkana)
|
||||
// <0=> Disabled
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </e4>
|
||||
// <o6> Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> Invalid
|
||||
// <e7> Use System PLL
|
||||
// <i> F_pll = M * F_in
|
||||
// <i> F_in must be in the range of 10 MHz to 25 MHz
|
||||
// <o8.0..4> M: PLL Multiplier Selection
|
||||
// <1-32><#-1>
|
||||
// <o8.5..6> P: PLL Divider Selection
|
||||
// <0=> 2
|
||||
// <1=> 4
|
||||
// <2=> 8
|
||||
// <3=> 16
|
||||
// <o8.7> DIRECT: Direct CCO Clock Output Enable
|
||||
// <o8.8> BYPASS: PLL Bypass Enable
|
||||
// </e7>
|
||||
// <o9> Select Input Clock for Main clock (Register: MAINCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </e1>
|
||||
// <e10> USB Clock Setup
|
||||
// <e11> Use USB PLL
|
||||
// <i> F_pll = M * F_in
|
||||
// <i> F_in must be in the range of 10 MHz to 25 MHz
|
||||
// <o12.0..1> Select Input Clock for usb_pllclkin (Register: USBPLLCLKSEL)
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <o13.0..4> M: PLL Multiplier Selection
|
||||
// <1-32><#-1>
|
||||
// <o13.5..6> P: PLL Divider Selection
|
||||
// <0=> 2
|
||||
// <1=> 4
|
||||
// <2=> 8
|
||||
// <3=> 16
|
||||
// <o13.7> DIRECT: Direct CCO Clock Output Enable
|
||||
// <o13.8> BYPASS: PLL Bypass Enable
|
||||
// </e11>
|
||||
// </e10>
|
||||
// <o14.0..7> System AHB Divider <0-255>
|
||||
// <i> 0 = is disabled
|
||||
// <o15.0> SYS Clock Enable
|
||||
// <o15.1> ROM Clock Enable
|
||||
// <o15.2> RAM Clock Enable
|
||||
// <o15.3> FLASH1 Clock Enable
|
||||
// <o15.4> FLASH2 Clock Enable
|
||||
// <o15.5> I2C Clock Enable
|
||||
// <o15.6> GPIO Clock Enable
|
||||
// <o15.7> CT16B0 Clock Enable
|
||||
// <o15.8> CT16B1 Clock Enable
|
||||
// <o15.9> CT32B0 Clock Enable
|
||||
// <o15.10> CT32B1 Clock Enable
|
||||
// <o15.11> SSP Clock Enable
|
||||
// <o15.12> UART Clock Enable
|
||||
// <o15.13> ADC Clock Enable
|
||||
// <o15.14> USB_REG Clock Enable
|
||||
// <o15.15> SWDT Clock Enable
|
||||
// <o15.16> IOCON Clock Enable
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSCLK_SETUP 1
|
||||
#define SYSOSC_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000
|
||||
#define WDTOSC_SETUP 0
|
||||
#define WDTOSCCTRL_Val 0x000000A0
|
||||
#define SYSPLLCLKSEL_Val 0x00000001
|
||||
#define SYSPLL_SETUP 1
|
||||
#define SYSPLLCTRL_Val 0x00000025
|
||||
#define MAINCLKSEL_Val 0x00000003
|
||||
|
||||
// ******** Code Red *********
|
||||
// * Changed USBCLK_SETUP to 1
|
||||
// ***************************
|
||||
#define USBCLK_SETUP 1
|
||||
#define USBPLL_SETUP 1
|
||||
#define USBPLLCLKSEL_Val 0x00000001
|
||||
#define USBPLLCTRL_Val 0x00000003
|
||||
#define SYSAHBCLKDIV_Val 0x00000001
|
||||
#define AHBCLKCTRL_Val 0x0001005F
|
||||
|
||||
/*--------------------- Memory Mapping Configuration -------------------------
|
||||
//
|
||||
// <e> Memory Mapping
|
||||
// <o1.0..1> System Memory Remap (Register: SYSMEMREMAP)
|
||||
// <0=> Bootloader mapped to address 0
|
||||
// <1=> RAM mapped to address 0
|
||||
// <2=> Flash mapped to address 0
|
||||
// <3=> Flash mapped to address 0
|
||||
// </e>
|
||||
*/
|
||||
#define MEMMAP_SETUP 0
|
||||
#define SYSMEMREMAP_Val 0x00000001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLUEN_Val), ~0x00000001))
|
||||
#error "USBPLLUEN: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF))
|
||||
#error "AHBCLKCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003))
|
||||
#error "SYSMEMREMAP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (SYSCLK_SETUP) /* System Clock Setup */
|
||||
#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
#else
|
||||
#define __WDT_OSC_CLK (1600000 / 2)
|
||||
#endif // WDTOSC_SETUP
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 2)
|
||||
#define __SYS_PLLCLKIN (__WDT_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#if (SYSPLL_SETUP) /* System PLL Setup */
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
#else
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1))
|
||||
#endif // SYSPLL_SETUP
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else // SYSCLK_SETUP
|
||||
#if (SYSAHBCLKDIV_Val == 0)
|
||||
#define __SYSTEM_CLOCK (0)
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__XTAL / SYSAHBCLKDIV_Val)
|
||||
#endif
|
||||
#endif // SYSCLK_SETUP
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__XTAL)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 400000; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = wdt_osc;
|
||||
} else {
|
||||
SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (SYSCLK_SETUP) /* System Clock Setup */
|
||||
#if (SYSOSC_SETUP) /* System Oscillator Setup */
|
||||
uint32_t i;
|
||||
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
#if (SYSPLL_SETUP) /* System PLL Setup */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
#endif
|
||||
#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
#endif
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
#endif
|
||||
|
||||
#if (USBCLK_SETUP) /* USB Clock Setup */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
#if (USBPLL_SETUP) /* USB PLL Setup */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
|
||||
#else
|
||||
LPC_SYSCON->USBCLKSEL = 0x01; /* Select Main Clock */
|
||||
#endif
|
||||
#else
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
|
||||
#endif
|
||||
|
||||
|
||||
#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */
|
||||
LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue